XC2S100E-6PQ208I Xilinx Inc, XC2S100E-6PQ208I Datasheet - Page 19

• Manufacturer Part Number: XC2S100E-6PQ208I
• Description: FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 208-Pin PQFP
• Manufacturer: Xilinx Inc

Specifications of XC2S100E-6PQ208I

• Package: 208PQFP
• Family Name: Spartan®-IIE
• Device Logic Cells: 2700
• Device Logic Units: 600
• Device System Gates: 100000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 146
• Ram Bits: 40960

Table 8: Boundary-Scan Instructions (Continued)
DS077-2 (v2.3) June 18, 2008
Product Specification
Boundary-Scan
USERCODE
RESERVED
TDI
Command
IDCODE
BYPASS
INTEST
JSTART
HIGHZ
IOB
IOB
IOB
IOB
IOB
IOB
IOB
R
IOB
Instruction Register
Code[4:0]
IOB
All other
Binary
00111
01000
01001
01010
01100
11111
codes
Register
Bypass
IOB
IOB
Figure 14: Spartan-IIE Family Boundary Scan Logic
Enables boundary-scan
Enables shifting out of
IOB
Disables output pins
Enables shifting out
INTEST operation
while enabling the
StartupClk is TCK
Clock the start-up
Enables BYPASS
Bypass Register
sequence when
Xilinx reserved
Description
USER code
instructions
ID Code
IOB
IOB
IOB
IOB
IOB
IOB
IOB
M
U
X
TDO
www.xilinx.com
IOB.Q
IOB.T
IOB.T
IOB.I
IOB.I
CAPTURE
SHIFT/
The public boundary-scan instructions are available prior to
configuration, except for USER1 and USER2. After configu-
ration, the public instructions remain available together with
any USERCODE instructions installed during the configura-
tion. While the SAMPLE/PRELOAD and BYPASS instruc-
tions are available during configuration, it is recommended
that boundary-scan operations not be performed during this
transitional period.
In addition to the test instructions outlined above, the
boundary-scan circuitry can be used to configure the
FPGA, and also to read back the configuration data.
To facilitate internal scan chains, the User Register provides
three outputs (Reset, Update, and Shift) that represent the
corresponding states in the boundary-scan internal state
machine.
Figure 14
scan logic. It includes three bits of Data Register per IOB,
the IEEE 1149.1 Test Access Port controller, and the
Instruction Register with decodes.
DATAOUT
DATA IN
CLOCK DATA
Spartan-IIE FPGA Family: Functional Description
REGISTER
1
0
1
0
1
0
1
0
1
0
is a diagram of the Spartan-IIE family boundary
D
D
D
D
D
Q
Q
Q
Q
Q
UPDATE
D
D
D
D
D
LE
LE
LE
LE
LE
sd
sd
sd
sd
sd
Q
Q
Q
Q
Q
0
1
1
0
1
0
0
1
1
0
EXTEST
DS001_09_032300
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