XC2S100E-6TQG144C Xilinx Inc, XC2S100E-6TQG144C Datasheet - Page 81

• Manufacturer Part Number: XC2S100E-6TQG144C
• Description: FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-IIEr

Specifications of XC2S100E-6TQG144C

• Package: 144TQFP
• Family Name: Spartan®-IIE
• Device Logic Cells: 2700
• Device Logic Units: 600
• Device System Gates: 100000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 102
• Ram Bits: 40960
• Number Of Logic Elements/cells: 2700
• Number Of Labs/clbs: 600
• Total Ram Bits: 40960
• Number Of I /o: 102
• Number Of Gates: 100000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1462

FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E)
DS077-4 (2.3) June 18, 2008
Product Specification
I/O, L#N
I/O, L#P
I/O, L#N
I/O, L#P
I/O
I/O
I/O, L#N
I/O, L#P
I/O, VREF
Bank 3,
L#N
I/O, L#P
I/O
I/O, L#N
I/O, L#P
I/O, L#N
I/O, L#P
I/O
I/O, VREF
Bank 3,
L#N
I/O (D6),
L#P
I/O (D5),
L#N_YY
I/O,
L#P_YY
Function Bank
Pad Name
R
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
V19
V20
V22
U22
U21
U20
U18
U19
R21
R22
R20
R18
R19
P22
P21
T21
T22
T20
T18
T19
Pin
200E, 300E,
200E, 300E,
200E, 300E,
200E, 300E,
200E, 300E,
200E, 300E,
200E, 300E,
200E, 300E,
200E, 300E,
200E, 300E,
150E, 300E,
150E, 300E,
XC2S150E,
XC2S150E,
XC2S100E,
XC2S100E,
XC2S100E,
XC2S100E,
XC2S150E,
400E, 600E
XC2S150E,
400E, 600E
XC2S150E,
XC2S150E,
XC2S100E,
XC2S100E,
XC2S300E,
400E, 600E
XC2S300E,
400E, 600E
Async.
Output
Option
LVDS
400E
400E
600E
600E
600E
600E
400E
400E
600E
600E
All
All
-
-
-
-
XC2S200E,
400E, 600E
XC2S600E
Option
300E,
V
All
All
REF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O, L40P_Y
I/O, L39P_Y
I/O, L37P_Y I/O, L49P_Y
I/O, VREF
I/O, VREF
L35N_YY
L35P_YY
I/O, L38P
I/O (D6),
I/O (D5),
L40N_Y
L39N_Y
L37N_Y
Bank 3,
Bank 3,
100E
L38N
L36N
L36P
I/O,
I/O,
I/O,
I/O,
www.xilinx.com
I/O
I/O
-
-
-
-
-
-
I/O, L54P_Y I/O, L58P_Y I/O, L58P_Y I/O, L58P_Y
I/O, L51P_Y I/O, L55P_Y I/O, L55P_Y I/O, L55P_Y I/O, L55P_Y
I/O, L50P_Y I/O, L54P_Y I/O, L54P_Y I/O, L54P_Y
I/O, VREF
I/O, VREF
I/O, L53N
I/O, L53P
I/O, L52N
I/O, L52P
L47N_YY
L47P_YY
I/O (D6),
I/O (D5),
L54N_Y
L51N_Y
L50N_Y
L49N_Y
Bank 3,
Bank 3,
L48N
150E
L48P
I/O,
I/O,
I/O,
I/O,
I/O
I/O
-
-
Device-Specific Pinouts: XC2S
I/O, L57P_Y I/O, L57P_Y
I/O, L56P_Y I/O, L56P_Y
I/O, VREF
I/O, VREF
I/O, VREF
I/O, L53N
L51N_YY
L51P_YY
I/O, L53P
I/O (D6),
I/O (D5),
L58N_Y
L57N_Y
L56N_Y
L55N_Y
L54N_Y
Bank 3,
Bank 3,
Bank 3,
200E
L52N
L52P
I/O,
I/O,
I/O,
I/O,
I/O
I/O
Spartan-IIE FPGA Family: Pinout Tables
-
-
I/O, L53P_Y
I/O, VREF
I/O, VREF
I/O, VREF
L51N_YY
L51P_YY
I/O (D6),
I/O (D5),
L58N_Y
L57N_Y
L56N_Y
L55N_Y
L54N_Y
L53N_Y
L52N_Y
L52P_Y
Bank 3,
Bank 3,
Bank 3,
300E
I/O,
I/O,
I/O,
I/O,
I/O,
I/O
I/O
I/O
I/O
I/O, VREF
I/O, VREF
I/O, VREF
I/O, L56N
I/O, L53N
L51N_YY
L51P_YY
I/O, L57P
I/O, L56P
I/O, L53P
I/O (D6),
L58N_Y
L55N_Y
L54N_Y
L52N_Y
L52P_Y
I/O (D5)
Bank 3,
Bank 3,
Bank 3,
400E
L57N
I/O,
I/O,
I/O,
I/O
I/O
I/O
I/O
I/O, L57P_Y
I/O, L56P_Y
I/O, L53P_Y
I/O, VREF
I/O, VREF
I/O, VREF
I/O, VREF
I/O, L58N
I/O, L58P
I/O, L54N
I/O, L54P
L51N_YY
L51P_YY
I/O (D6),
I/O (D5),
L57N_Y
L56N_Y
L55N_Y
L53N_Y
L52N_Y
L52P_Y
Bank 3,
Bank 3,
Bank 3,
Bank 3,
600E
I/O,
I/O,
I/O
I/O
I/O
I/O
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