XC2S50E-6FT256I Xilinx Inc, XC2S50E-6FT256I Datasheet - Page 53

• Manufacturer Part Number: XC2S50E-6FT256I
• Description: FPGA Spartan®-IIE Family 50K Gates 1728 Cells 357MHz 0.15um Technology 1.8V 256-Pin FTBGA
• Manufacturer: Xilinx Inc

Specifications of XC2S50E-6FT256I

• Package: 256FTBGA
• Family Name: Spartan®-IIE
• Device Logic Cells: 1728
• Device Logic Units: 384
• Device System Gates: 50000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 182
• Ram Bits: 32768

DS077-4 (2.3) June 18, 2008
Introduction
This section describes how the various pins on a
Spartan
component packages, and provides device-specific thermal
characteristics. Spartan-IIE FPGAs are available in both
standard and Pb-free, RoHS versions of each package, with
the Pb-free version adding a “G” to the middle of the
package code. Except for the thermal characteristics, all
information for the standard package applies equally to the
Pb-free package.
Pin Definitions
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DS077-4 (2.3) June 18, 2008
Product Specification
GCK0, GCK1, GCK2,
GCK3
DLL
M0, M1, M2
CCLK
PROGRAM
DONE
INIT
DOUT/BUSY
Pad Name
®
-IIE FPGA connect within the supported
Dedicated
Pin
Yes
Yes
Yes
Yes
No
No
No
No
R
Input or Output
(Open-drain)
Bidirectional
Bidirectional
Direction
Output
Input
Input
Input
Input
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Clock input pins that connect to Global Clock buffers or DLL
inputs. These pins become user inputs when not needed for
clocks.
Clock input pins that connect to DLL input or feedback clocks.
Differential clock input (N input of pair) when paired with adjacent
GCK input. Becomes a user I/O when not needed for clocks.
Mode pins used to specify the configuration mode.
The configuration Clock I/O pin. It is an input for Slave Parallel
and Slave Serial modes, and output in Master Serial mode. After
configuration, it is an input only with Don’t Care logic levels.
Initiates a configuration sequence when asserted Low.
Indicates that configuration loading is complete, and that the
start-up sequence is in progress. The output may be open drain.
When Low, indicates that the configuration memory is being
cleared. Goes High to indicate the end of initialization. Goes back
Low to indicate a CRC error. This pin becomes a user I/O after
configuration.
In Slave Parallel mode, BUSY controls the rate at which
configuration data can be loaded. It is not needed below 50 MHz.
This pin becomes a user I/O after configuration unless the Slave
Parallel port is retained.
In serial modes, DOUT provides configuration data to
downstream devices in a daisy-chain. This pin becomes a user
I/O after configuration.
0
Spartan-IIE FPGA Family:
Pinout Tables
Product Specification
Pin Types
Most pins on a Spartan-IIE FPGA are general-purpose,
user-defined I/O pins. There are, however, different
functional types of pins on Spartan-IIE FPGA packages, as
outlined below.
Description
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