XC2V2000-5FF896I Xilinx Inc, XC2V2000-5FF896I Datasheet - Page 32
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XC2V2000-5FF896I
Manufacturer Part Number
XC2V2000-5FF896I
Description
FPGA Virtex-II™ Family 2M Gates 24192 Cells 750MHz 0.15um/0.12um (CMOS) Technology 1.5V 896-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-IIr
Datasheet
1.XC2V250-4FGG256C.pdf
(318 pages)
Specifications of XC2V2000-5FF896I
Package
896FCBGA
Family Name
Virtex-IIÂ
Device Logic Units
24192
Device System Gates
2000000
Number Of Registers
21504
Maximum Internal Frequency
750 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
624
Ram Bits
1032192
Number Of Labs/clbs
2688
Total Ram Bits
1032192
Number Of I /o
624
Number Of Gates
2000000
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2V2000-5FF896I
Manufacturer:
XilinxInc
Quantity:
3 000
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3. “NO_CHANGE”
Control Pins and Attributes
Virtex-II SelectRAM memory has two independent ports
with the control signals described in
inputs including the clock have an optional inversion.
Table 17: Control Functions
DS031-2 (v3.5) November 5, 2007
Product Specification
RAM Contents
Control Signal
The “NO_CHANGE” option maintains the content of the
output registers, regardless of the write operation. The
clock edge during the write mode has no effect on the
content of the data output register DO. When the port is
configured as “NO_CHANGE”, only a read operation
loads a new value in the output register DO, as shown in
Figure
Data_out
Address
Data_in
Data_in
CLK
SSR
CLK
WE
EN
WE
33.
R
Figure 33: NO_CHANGE Mode
DI
New
Old
aa
Enable affects Read, Write, Set, Reset
Internal
Memory
Set DO register to SRVAL (attribute)
Read and Write Clock
Last Read Cycle Content (no change)
DO
Write Enable
Function
Table
No change during write
New
17. All control
DS031_12_102000
www.xilinx.com
Initial memory content is determined by the INIT_xx
attributes. Separate attributes determine the output register
value after device configuration (INIT) and SSR is asserted
(SRVAL). Both attributes (INIT_B and SRVAL) are available
for each port when a block SelectRAM resource is config-
ured as dual-port RAM.
Locations
Virtex-II SelectRAM memory blocks are located in either
four or six columns. The number of blocks per column
depends of the device array size and is equivalent to the
number of CLBs in a column divided by four. Column loca-
tions are shown in
Table 18: SelectRAM Memory Floor Plan
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
XC2V250
XC2V500
XC2V40
XC2V80
Device
Virtex-II Platform FPGAs: Functional Description
Columns
Table
2
2
4
4
4
4
4
6
6
6
6
18.
Per Column
SelectRAM Blocks
10
12
14
16
20
24
28
2
4
6
8
Module 2 of 4
Total
120
144
168
24
32
40
48
56
96
4
8
24
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