XC2V500-6FG456C Xilinx Inc, XC2V500-6FG456C Datasheet - Page 27

• Manufacturer Part Number: XC2V500-6FG456C
• Description: FPGA Virtex-II™ Family 500K Gates 6912 Cells 820MHz 0.15um/0.12um (CMOS) Technology 1.5V 456-Pin FBGA
• Manufacturer: Xilinx Inc

Specifications of XC2V500-6FG456C

• Package: 456FBGA
• Family Name: Virtex-II™
• Device Logic Units: 6912
• Device System Gates: 500000
• Number Of Registers: 6144
• Maximum Internal Frequency: 820 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 264
• Ram Bits: 589824

Sum of Products
Each Virtex-II slice has a dedicated OR gate named ORCY,
ORing together outputs from the slices carryout and the ORCY
from an adjacent slice. The ORCY gate with the dedicated
Sum of Products (SOP) chain are designed for implementing
LUTs and MUXCYs can implement large AND gates or
other combinatorial logic functions.
DS031-2 (v3.5) November 5, 2007
Product Specification
4
4
4
4
R
LUT
LUT
LUT
LUT
4
4
4
4
MUXCY
MUXCY
MUXCY
MUXCY
ORCY
Slice 1
Slice 0
V
CC
4
4
4
4
LUT
LUT
LUT
LUT
Figure 26: Wide-Input AND Gate (16 Inputs)
LUT
LUT
LUT
LUT
Figure 26
Figure 25: Horizontal Cascade Chain
MUXCY
MUXCY
MUXCY
MUXCY
ORCY
Slice 2
Slice 3
V
illustrates
CC
“0”
“0”
“0”
CLB
0
0
0
0
MUXCY
MUXCY
MUXCY
MUXCY
www.xilinx.com
V CC
1
1
1
1
4
4
4
4
Slice
Slice
large, flexible SOP chains. One input of each ORCY is con-
nected through the fast SOP chain to the output of the previous
ORCY in the same slice row. The second input is connected to
the output of the top MUXCY in the same slice, as shown in
Figure
LUT and MUXCY resources configured as a 16-input AND
gate.
LUT
LUT
LUT
LUT
OUT
25.
Virtex-II Platform FPGAs: Functional Description
MUXCY
MUXCY
MUXCY
MUXCY
ORCY
Slice 0
Slice 1
V
CC
16
4
4
4
4
LUT
LUT
LUT
LUT
AND
DS031_41_110600
MUXCY
MUXCY
MUXCY
MUXCY
OUT
ORCY
Slice 3
Slice 2
V
CC
CLB
ds031_64_110300
SOP
Module 2 of 4
19