XC2V80-4FG256C Xilinx Inc, XC2V80-4FG256C Datasheet - Page 11

• Manufacturer Part Number: XC2V80-4FG256C
• Description: FPGA Virtex-II™ Family 80K Gates 1152 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 256-Pin FBGA
• Manufacturer: Xilinx Inc

Specifications of XC2V80-4FG256C

• Package: 256FBGA
• Family Name: Virtex-II™
• Device Logic Units: 1152
• Device System Gates: 80000
• Number Of Registers: 1024
• Maximum Internal Frequency: 650 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 120
• Ram Bits: 147456

The DDR mechanism shown in
ror a copy of the clock on the output. This is useful for prop-
agating a clock along the data that has an identical delay. It
is also useful for multiple clock generation, where there is a
unique clock driver for every clock load. Virtex-II devices
can produce many copies of a clock with very little skew.
Each group of two registers has a clock enable signal (ICE
for the input registers, OCE for the output registers, and
TCE for the 3-state registers). The clock enable signals are
active High by default. If left unconnected, the clock enable
for that storage element defaults to the active state.
Each IOB block has common synchronous or asynchronous
set and reset (SR and REV signals).
SR forces the storage element into the state specified by the
SRHIGH or SRLOW attribute. SRHIGH forces a logic “1”.
SRLOW forces a logic “0”. When SR is used, a second input
(REV) forces the storage element into the opposite state. The
reset condition predominates over the set condition. The ini-
tial state after configuration or global initialization state is
defined by a separate INIT0 and INIT1 attribute. By default,
the SRLOW attribute forces INIT0, and the SRHIGH attribute
forces INIT1.
DS031-2 (v3.5) November 5, 2007
Product Specification
CLOCK
R
D1
D2
CLK1
CLK2
Figure 3
(50/50 duty cycle clock)
Q1
Q2
can be used to mir-
Figure 3: Double Data Rate Registers
DDR MUX
FDDR
www.xilinx.com
Q
For each storage element, the SRHIGH, SRLOW, INIT0,
and INIT1 attributes are independent. Synchronous or
asynchronous set / reset is consistent in an IOB block.
All the control signals have independent polarity. Any
inverter placed on a control input is automatically absorbed.
Each register or latch (independent of all other registers or
latches) (see
•
•
•
•
•
•
•
The synchronous reset overrides a set, and an asynchro-
nous clear overrides a preset.
180° 0°
No set or reset
Synchronous set
Synchronous reset
Synchronous set and reset
Asynchronous set (preset)
Asynchronous reset (clear)
Asynchronous set and reset (preset and clear)
DCM
Virtex-II Platform FPGAs: Functional Description
Figure
D1
D2
CLK1
CLK2
4) can be configured as follows:
Q1
Q2
DDR MUX
FDDR
DS031_26_100900
Q
Module 2 of 4
3