XC3S100E-4CPG132C Xilinx Inc, XC3S100E-4CPG132C Datasheet - Page 46
![FPGA Spartan®-3E Family 100K Gates 2160 Cells 572MHz 90nm (CMOS) Technology 1.2V 132-Pin CSBGA](/photos/6/70/67095/pk373-cp132_sml.jpg)
XC3S100E-4CPG132C
Manufacturer Part Number
XC3S100E-4CPG132C
Description
FPGA Spartan®-3E Family 100K Gates 2160 Cells 572MHz 90nm (CMOS) Technology 1.2V 132-Pin CSBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S100E-4CPG132C
Package
132CSBGA
Family Name
Spartan®-3E
Device Logic Cells
2160
Device Logic Units
240
Device System Gates
100000
Number Of Registers
1920
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
83
Ram Bits
73728
Number Of Logic Elements/cells
2160
Number Of Labs/clbs
240
Total Ram Bits
73728
Number Of I /o
83
Number Of Gates
100000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
132-TFBGA, CSPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1515
Available stocks
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Price
Company:
Part Number:
XC3S100E-4CPG132C
Manufacturer:
Xilinx Inc
Quantity:
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Part Number:
XC3S100E-4CPG132C
Manufacturer:
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Functional Description
The BCIN and BCOUT ports have associated dedicated
routing that connects adjacent multipliers within the same
column. Via the cascade connection, the BCOUT port of
one multiplier block drives the BCIN port of the multiplier
block directly above it. There is no connection to the BCIN
port of the bottom-most multiplier block in a column or a
connection from the BCOUT port of the top-most block in a
column. As an example,
cade capability within the XC3S100E FPGA, which has a
single column of multiplier, four blocks tall. For clarity, the
figure omits the register control inputs.
46
Figure 39: Multiplier Cascade Connection
B_INPUT = CASCADE
B_INPUT = CASCADE
B_INPUT = CASCADE
B_INPUT = DIRECT
Figure 39
A
B
A
B
A
B
A
B
BCOUT
BCOUT
BCOUT
BCOUT
shows the multiplier cas-
BCIN
BCIN
BCIN
BCIN
DS312-2_30_021505
P
P
P
P
www.xilinx.com
When using the BREG register, the cascade connection
forms a shift register structure typically used in DSP algo-
rithms such as direct-form FIR filters. When the BREG reg-
ister is omitted, the cascade structure essentially feeds the
same input value to more than one multiplier. This parallel
connection serves to create wide-input multipliers, imple-
ment transpose FIR filters, and is used in any application
that requires that several multipliers have the same input
value.
Multiplier/Block RAM Interaction
Each multiplier is located adjacent to an 18 Kbit block RAM
and shares some interconnect resources. Configuring an
18 Kbit block RAM for 36-bit wide data (512 x 36 mode) pre-
vents use of the associated dedicated multiplier.
The upper 16 bits of the ‘A’ multiplicand input are shared
with the upper 16 bits of the block RAM’s Port A Data input.
Similarly, the upper 16 bits of the ‘B’ multiplicand input are
shared with Port B’s data input. See also
page
64.
DS312-2 (v3.8) August 26, 2009
Product Specification
Figure 48,
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