XC3S1500-4FG320C Xilinx Inc, XC3S1500-4FG320C Datasheet - Page 142
![no-image](/images/no-image-200.jpg)
XC3S1500-4FG320C
Manufacturer Part Number
XC3S1500-4FG320C
Description
FPGA Spartan®-3 Family 1.5M Gates 29952 Cells 630MHz 90nm Technology 1.2V 320-Pin FBGA
Manufacturer
Xilinx Inc
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S1500-4FG320C
Package
320FBGA
Family Name
Spartan®-3
Device Logic Units
29952
Device System Gates
1500000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
221
Ram Bits
589824
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S1500-4FG320C
Manufacturer:
XILINX
Quantity:
745
Part Number:
XC3S1500-4FG320C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
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Spartan-3 FPGA Family: Pinout Descriptions
FT256: 256-lead Fine-pitch Thin Ball
Grid Array
The 256-lead fine-pitch thin ball grid array package, FT256,
supports three different Spartan-3 devices, including the
XC3S200, the XC3S400, and the XC3S1000. The footprints
for all three devices are identical, as shown in
Figure
All the package pins appear in
bank number, then by pin name. Pairs of pins that form a dif-
ferential I/O pair appear together in the table. The table also
shows the pin number for each pin and the pin type, as
defined earlier.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web-
site at
sheets/s3_pin.zip
Pinout Table
Table 95: FT256 Package Pinout
142
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
46.
http://www.xilinx.com/support/documentation/data_
IO
IO
IO/VREF_0
IO/VREF_0
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L25N_0
IO_L25P_0
IO_L27N_0
IO_L27P_0
IO_L28N_0
IO_L28P_0
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L31P_0/VREF_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
VCCO_0
VCCO_0
VCCO_0
IO
IO
.
XC3S1000
Pin Name
XC3S200
XC3S400
Table 95
Number
FT256
and are sorted by
A12
Pin
A5
A7
A3
D5
B4
A4
C5
B5
E6
D6
C6
B6
E7
D7
C7
B7
D8
C8
B8
A8
E8
A9
F7
F8
Table 95
VCCO
VCCO
VCCO
VREF
VREF
VREF
GCLK
GCLK
Type
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
www.xilinx.com
and
Table 95: FT256 Package Pinout (Continued)
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO
IO/VREF_1
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L10N_1/VREF_1
IO_L10P_1
IO_L27N_1
IO_L27P_1
IO_L28N_1
IO_L28P_1
IO_L29N_1
IO_L29P_1
IO_L30N_1
IO_L30P_1
IO_L31N_1/VREF_1
IO_L31P_1
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
VCCO_1
VCCO_1
VCCO_1
IO
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L16N_2
IO_L16P_2
IO_L17N_2
IO_L17P_2/VREF_2
IO_L19N_2
IO_L19P_2
IO_L20N_2
IO_L20P_2
IO_L21N_2
IO_L21P_2
IO_L22N_2
IO_L22P_2
IO_L23N_2/VREF_2
IO_L23P_2
IO_L24N_2
IO_L24P_2
XC3S1000
Pin Name
XC3S200
XC3S400
DS099-4 (v2.5) December 4, 2009
Product Specification
Number
FT256
G16
G12
G13
G14
G15
C10
D12
A14
B14
A13
B13
B12
C12
D11
E11
B11
C11
D10
E10
A10
B10
B16
C16
C15
D14
D15
D16
E13
E14
E15
E16
F10
F12
F13
F14
F15
Pin
C9
D9
E9
F9
VCCO
VCCO
VCCO
VREF
VREF
VREF
GCLK
GCLK
VREF
VREF
Type
DCI
DCI
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
R
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