XC3S400-4FGG456C Xilinx Inc, XC3S400-4FGG456C Datasheet - Page 90
![FPGA Spartan®-3 Family 400K Gates 8064 Cells 630MHz 90nm Technology 1.2V 456-Pin FBGA](/photos/6/72/67297/xc3s400-4fgg456c_sml.jpg)
XC3S400-4FGG456C
Manufacturer Part Number
XC3S400-4FGG456C
Description
FPGA Spartan®-3 Family 400K Gates 8064 Cells 630MHz 90nm Technology 1.2V 456-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S400-4FGG456C
Package
456FBGA
Family Name
Spartan®-3
Device Logic Units
8064
Device System Gates
400000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
264
Ram Bits
294912
Number Of Logic Elements/cells
8064
Number Of Labs/clbs
896
Total Ram Bits
294912
Number Of I /o
264
Number Of Gates
400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
456-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1341
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S400-4FGG456C
Manufacturer:
XILINX
Quantity:
670
Part Number:
XC3S400-4FGG456C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Spartan-3 FPGA Family: DC and Switching Characteristics
Phase Shifter (PS)
Phase shifter operation is only supported if the DLL is in low-frequency mode, see
software version 10.1.03 (or later).
Table 61: Recommended Operating Conditions for the PS in Variable Phase Mode
Table 62: Switching Characteristics for the PS in Variable or Fixed Phase Shift Mode
90
Notes:
1.
2.
Operating Frequency Ranges
PSCLK_FREQ
(F
Input Pulse Requirements
PSCLK_PULSE
Phase Shifting Range
FINE_SHIFT_RANGE
Lock Time
LOCK_DLL_PS
LOCK_DLL_PS_FX
PSCLK
The numbers in this table are based on the operating conditions set forth in
The PS specifications in this table apply when the PS attribute CLKOUT_PHASE_SHIFT= VARIABLE or FIXED.
Symbol
Symbol
)
Frequency for the
PSCLK input
PSCLK pulse width
as a percentage of
the PSCLK period
Description
Phase shift range
When using the PS in conjunction
with the DLL: The time from
deassertion at the DCM’s Reset
input to the rising transition at its
LOCKED output. When the DCM
is locked, the CLKIN and CLKFB
signals are in phase.
When using the PS in conjunction
with the DLL and DFS: The time
from deassertion at the DCM’s
Reset input to the rising transition
at its LOCKED output. When the
DCM is locked, the CLKIN and
CLKFB signals are in phase.
Description
Low
Frequency Mode/
F
CLKIN
F
F
Low
CLKIN
CLKIN
www.xilinx.com
Range
60 MHz < F
18 MHz < F
30 MHz < F
40 MHz < F
50 MHz < F
< 100 MHz
> 100 MHz
Frequency Mode/
F
CLKIN
CLKIN
Low
CLKIN
CLKIN
CLKIN
CLKIN
Low
Range
< 165 MHz
< 30 MHz
< 40 MHz
< 50 MHz
< 60 MHz
40%
45%
Table 31
Min
1
-5
and
Table
60%
55%
Max
167
Speed Grade
Table
Min
-
-
-
-
-
-
-
57. Fixed phase shift requires ISE
-5
61.
DS099-3 (v2.5) December 4, 2009
10.40
Speed Grade
Max
10.0
3.28
2.56
1.60
1.00
0.88
40%
45%
Min
1
-4
Min
Product Specification
-
-
-
-
-
-
-
60%
55%
Max
167
-4
10.40
Max
10.0
3.28
2.56
1.60
1.00
0.88
Units
MHz
Units
-
-
ms
ms
ms
ms
ms
ms
ns
R