XC3S400-4TQG144C Xilinx Inc, XC3S400-4TQG144C Datasheet - Page 125
![FPGA Spartan®-3 Family 400K Gates 8064 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP](/photos/6/70/67094/144tqfp_sml.jpg)
XC3S400-4TQG144C
Manufacturer Part Number
XC3S400-4TQG144C
Description
FPGA Spartan®-3 Family 400K Gates 8064 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S400-4TQG144C
Package
144TQFP
Family Name
Spartan®-3
Device Logic Units
8064
Device System Gates
400000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
97
Ram Bits
294912
Package / Case
144-TQFP, 144-VQFP
Mounting Type
Surface Mount
Voltage - Supply
1.14 V ~ 3.465 V
Operating Temperature
0°C ~ 85°C
Number Of I /o
97
Number Of Logic Elements/cells
896
Number Of Gates
400000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S400-4TQG144C
Manufacturer:
XILINX
Quantity:
1 445
Company:
Part Number:
XC3S400-4TQG144C
Manufacturer:
XILINX
Quantity:
150
Part Number:
XC3S400-4TQG144C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Table 86: VQ100 Package Pinout
Table 87: User I/Os Per Bank in VQ100 Package
DS099-4 (v2.5) December 4, 2009
Product Specification
Package Edge
Bank
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
7
7
7
7
Bottom
Right
Left
Top
R
IO_L23P_7
IO_L40N_7/VREF_7
IO_L40P_7
VCCO_7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
Pin Name
XC3S200
XC3S50
I/O Bank
0
1
2
3
4
5
6
7
Maximum
VQ100 Pin
Number
I/O
10
6
7
8
8
8
8
8
P12
P11
P10
P20
P29
P41
P56
P66
P73
P82
P95
P33
P58
P84
P18
P8
P6
P3
P7
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCO
VREF
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I/O
I/O
www.xilinx.com
I/O
1
2
5
5
0
0
4
5
Table 86: VQ100 Package Pinout
User I/Os by Bank
Table 87
tributed between the eight I/O banks on the VQ100 pack-
age.
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
DUAL
Bank
N/A
N/A
N/A
0
0
0
0
6
6
0
0
All Possible I/O Pins by Type
indicates how the available user-I/O pins are dis-
Spartan-3 FPGA Family: Pinout Descriptions
VCCINT
VCCINT
VCCINT
CCLK
DONE
HSWAP_EN
M0
M1
M2
PROG_B
TCK
TDI
TDO
TMS
DCI
2
2
2
2
2
0
2
2
Pin Name
XC3S200
XC3S50
VREF
1
1
1
1
0
0
2
1
VQ100 Pin
Number
P100
P45
P69
P93
P52
P51
P98
P25
P24
P26
P99
P77
P76
P78
GCLK
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
VCCINT
VCCINT
VCCINT
2
2
0
0
2
2
0
0
JTAG
JTAG
JTAG
JTAG
Type
125