XC3S4000-5FGG676C Xilinx Inc, XC3S4000-5FGG676C Datasheet - Page 193
![FPGA Spartan®-3 Family 4M Gates 62208 Cells 725MHz 90nm Technology 1.2V 676-Pin FBGA](/photos/6/73/67300/b-676_sml.jpg)
XC3S4000-5FGG676C
Manufacturer Part Number
XC3S4000-5FGG676C
Description
FPGA Spartan®-3 Family 4M Gates 62208 Cells 725MHz 90nm Technology 1.2V 676-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S4000-5FGG676C
Package
676FBGA
Family Name
Spartan®-3
Device Logic Units
62208
Device System Gates
4000000
Maximum Internal Frequency
725 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
489
Ram Bits
1769472
Number Of Logic Elements/cells
62208
Number Of Labs/clbs
6912
Total Ram Bits
1769472
Number Of I /o
489
Number Of Gates
4000000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S4000-5FGG676C
Manufacturer:
XILINX
Quantity:
1
Company:
Part Number:
XC3S4000-5FGG676C
Manufacturer:
XILINX
Quantity:
50
Company:
Part Number:
XC3S4000-5FGG676C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S4000-5FGG676C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Table 106: FG900 Package Pinout (Continued)
Table 107: User I/Os Per Bank for XC3S2000 in FG900 Package
Table 108: User I/Os Per Bank for XC3S4000 and XC3S5000 in FG900 Package
DS099-4 (v2.5) December 4, 2009
Product Specification
VCCAUX PROG_B
VCCAUX TCK
VCCAUX TDI
VCCAUX TDO
VCCAUX TMS
Bank
Bottom
Bottom
Edge
Edge
Right
Right
Left
Left
Top
Top
R
XC3S2000
Pin Name
Bank
Bank
I/O
I/O
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
PROG_B
TCK
TDI
TDO
TMS
XC3S4000
XC3S5000
Pin Name
Maximum
Maximum
I/O
I/O
71
71
69
71
72
71
69
71
79
79
79
79
80
79
79
79
Number
FG900
C28
B28
A28
Pin
C3
B3
CONFIG
I/O
I/O
62
62
61
62
57
55
60
62
70
70
71
70
65
63
70
70
JTAG
JTAG
JTAG
JTAG
Type
www.xilinx.com
User I/Os by Bank
Table 107
tributed between the eight I/O banks for the XC3S2000 in
the FG900 package. Similarly,
available user-I/O pins are distributed between the eight I/O
banks for the XC3S4000 and XC3S5000 in the FG900
package.
DUAL
DUAL
0
0
0
0
6
6
0
0
0
0
0
0
6
6
0
0
All Possible I/O Pins by Type
All Possible I/O Pins by Type
indicates how the available user-I/O pins are dis-
Spartan-3 FPGA Family: Pinout Descriptions
DCI
DCI
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
VREF
VREF
Table 108
5
5
6
7
5
6
7
7
5
5
6
7
5
6
7
7
shows how the
GCLK
GCLK
2
2
0
0
2
2
0
0
2
2
0
0
2
2
0
0
193