XC3S700A-4FG400C Xilinx Inc, XC3S700A-4FG400C Datasheet - Page 6

• Manufacturer Part Number: XC3S700A-4FG400C
• Description: FPGA Spartan®-3A Family 700K Gates 13248 Cells 667MHz 90nm Technology 1.2V 400-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Ar

Specifications of XC3S700A-4FG400C

• Package: 400FBGA
• Family Name: Spartan®-3A
• Device Logic Units: 13248
• Device System Gates: 700000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 311
• Ram Bits: 368640
• Number Of Logic Elements/cells: 13248
• Number Of Labs/clbs: 1472
• Total Ram Bits: 368640
• Number Of I /o: 311
• Number Of Gates: 700000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 122-1514 - KIT STARTER W/SPARTAN-3A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Extended Spartan-3A Family Documentation
Complete and up-to-date documentation of the Extended Spartan-3A family of FPGAs is available on the Xilinx website. The
following files are also available for download:
DS529, Spartan-3A FPGA Data Sheet
DS610, Spartan-3A DSP FPGA Data Sheet
DS557, Spartan-3AN FPGA Data Sheet
These data sheets contain DC and Switching Characteristic
specifications and pinouts for the Extended Spartan-3A
family.
UG331, Spartan-3 Generation FPGA User Guide
This guide includes chapters on:
UG332, Spartan-3 Generation Configuration User Guide
This guide includes chapters on:
Revision History
The following table shows the revision history for this document:
DS706 (v1.1) February 2, 2011
Product Specification
08/04/08
01/29/10
02/02/11
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Date
Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
Configurable Logic Blocks (CLBs)
I/O Resources
Embedded Multiplier Blocks
Programmable Interconnect
ISE Design Tools
IP Cores
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
Powering FPGAs
Power Management
Configuration Overview
R
Version
1.0.1
1.0
1.1
Initial Xilinx release.
Corrected typo in the slice count for XC3SD1800A in
Updated for new Spartan-3AN family part/package combinations: XC3S50AN and XC3S400AN in
FT(G)256 package, and XC3S1400AN in FG(G)484 package. Removed footnote for maximum user
I/O for XC3S50A/AN in
Temperature table.
Table
www.xilinx.com
1. Updated
UG333, Spartan-3AN FPGA In-System Flash User Guide
This guide provides information for Spartan-3AN FPGA
applications that write to or read from the In-System flash
memory after configuration:
UG431, XtremeDSP DSP48A for Spartan-3A DSP
FPGAs User Guide
This guide describes the DSP48A slices and the DSP48A
pre-adder.
Extended Spartan-3A Family Starter Kits
For specific hardware examples, see the Starter Kit boards
for the Extended Spartan-3A family. The following web page
has links to various boards for each family, including design
examples and the user guides:
http://www.xilinx.com/products/boards/s3_sk_promo.htm
Description of Revisions
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Table 2
Detailed Descriptions by Mode
ISE iMPACT Programming Examples
MultiBoot Reconfiguration
Design Authentication using Device DNA
SPI_ACCESS interface
In-System flash memory architecture
Read, program, and erase commands
Status registers
Sector Protection and Sector Lockdown features
Security Register with Unique Identifier
content and table notes. Updated Device
Table
Extended Spartan-3A Family Overview
1.
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