XC3SD3400A-4CS484I Xilinx Inc, XC3SD3400A-4CS484I Datasheet - Page 84
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XC3SD3400A-4CS484I
Manufacturer Part Number
XC3SD3400A-4CS484I
Description
FPGA Spartan®-3A Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 484-Pin LCSBGA
Manufacturer
Xilinx Inc
Datasheet
1.XC3SD3400A-4FGG676C.pdf
(101 pages)
Specifications of XC3SD3400A-4CS484I
Package
484LCSBGA
Family Name
Spartan®-3A
Device Logic Units
53712
Device System Gates
3400000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
309
Ram Bits
2322432
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3SD3400A-4CS484I
Manufacturer:
XILINX
Quantity:
290
Company:
Part Number:
XC3SD3400A-4CS484I
Manufacturer:
XilinxInc
Quantity:
3 000
User I/Os by Bank
Table 67
AWAKE pin is counted as a dual-purpose I/O.
Table 67: User I/Os Per Bank for the XC3SD1800A in the FG676 Package
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
Top
Right
Bottom
Left
Package
TOTAL
28 VREF are on INPUT pins.
Edge
indicates how the available user-I/O pins are distributed between the four I/O banks on the FG676 package. The
I/O Bank
0
1
2
3
Maximum I/Os
Input-Only
and
128
130
129
132
519
314
I/O
82
67
68
97
www.xilinx.com
INPUT
Spartan-3A DSP FPGA Family: Pinout Descriptions
28
15
21
18
82
All Possible I/O Pins by Type
DUAL
30
21
52
1
0
VREF
10
11
39
9
9
(1)
CLK
32
8
8
8
8
84