XC5VLX110T-1FF1136C Xilinx Inc, XC5VLX110T-1FF1136C Datasheet - Page 176
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XC5VLX110T-1FF1136C
Manufacturer Part Number
XC5VLX110T-1FF1136C
Description
FPGA Virtex®-5 Family 110592 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110T-1FF1136C
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
110592
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
5455872
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
5455872
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5122-1586 - BOARD EVAL FOR VIRTEX-5 ML555HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110T-1FF1136C
Manufacturer:
XILINX
Quantity:
2
Company:
Part Number:
XC5VLX110T-1FF1136C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX110T-1FF1136C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
- Current page: 176 of 385
- Download datasheet (14Mb)
Chapter 5: Configurable Logic Blocks (CLBs)
X-Ref Target - Figure 5-4
176
CLK
DX
CX
SR
CE
BX
AX
D6
D5
D4
D3
D2
D1
C6
C5
C4
C3
C2
C1
B6
B5
B4
B3
B2
B1
A6
A5
A4
A3
A2
A1
A6
A5
A4
A3
A2
A1
A6
A5
A4
A3
A2
A1
A6
A5
A4
A3
A2
A1
A6
A5
A4
A3
A2
A1
LUT
ROM
LUT
ROM
LUT
ROM
LUT
ROM
O6
O5
O6
O5
O6
O5
O6
O5
Each CLB can contain zero or one SLICEM. Every other CLB column contains a SLICEMs.
In addition, the two CLB columns to the left of the DSP48E columns both contain a SLICEL
and a SLICEM.
Figure 5-4: Diagram of SLICEL
COUT
www.xilinx.com
0/1
CIN
DX
CX
BX
AX
D
C
B
A
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Reset Type
Sync
Async
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
SR REV
SR REV
SR REV
SR REV
Q
Q
Q
Q
UG190_5_04_032606
DMUX
D
DQ
CMUX
C
CQ
BMUX
B
BQ
AMUX
A
AQ
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