XC5VLX50-1FF676I Xilinx Inc, XC5VLX50-1FF676I Datasheet - Page 51
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XC5VLX50-1FF676I
Manufacturer Part Number
XC5VLX50-1FF676I
Description
FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-1FF676I
Package
676FCBGA
Family Name
Virtex®-5
Device Logic Units
46080
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
440
Ram Bits
1769472
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
1769472
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF676-500-G - BOARD DEV VIRTEX 5 FF676HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Configuration Switching Characteristics
Table 70: Configuration Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
Power-up Timing Characteristics
T
T
T
T
Master/Slave Serial Mode Programming Switching
T
T
T
F
F
F
SelectMAP Mode Programming Switching
T
T
T
T
T
T
F
F
F
Boundary-Scan Port Timing Specifications
T
T
T
F
F
PL
POR
ICCK
PROGRAM
DCCK
DSCCK
CCO
MCCK
MCCKTOL
MSCCK
SMDCCK
SMCSCCK
SMCCKW
SMCKCSO
SMCO
SMCKBY
SMCCK
RBCCK
MCCKTOL
TAPTCK
TCKTAP
TCKTDO
TCK
TCKB
/T
/T
CCKD
/T
/T
SCCKD
/T
SMCCKD
SMWCCK
SMCCKCS
Symbol
Program Latency
Power-on-Reset
CCLK (output) delay
Program Pulse Width
DIN Setup/Hold, slave mode
DIN Setup/Hold, master mode
DOUT
Maximum Frequency, master mode with
respect to nominal CCLK.
Frequency Tolerance, master mode with
respect to nominal CCLK.
Slave mode external CCLK
SelectMAP Data Setup/Hold
CS_B Setup/Hold
RDWR_B Setup/Hold
CSO_B clock to out
(330 Ω pull-up resistor required)
CCLK to DATA out in readback
CCLK to BUSY out in readback
Maximum Frequency with respect to nominal
CCLK.
Maximum Readback Frequency with respect
to nominal CCLK
Frequency Tolerance with respect to nominal
CCLK.
TMS and TDI Setup time before TCK
TMS and TDI Hold time after TCK
TCK falling edge to TDO output valid
Maximum configuration TCK clock frequency
Maximum boundary-scan TCK clock
frequency
(1)
(1)
Description
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
400
250
100
±50
100
100
±50
4.0
0.0
4.0
0.0
7.5
3.0
0.5
3.0
0.5
8.0
0.5
7.5
9.0
1.0
2.0
10
50
10
60
66
66
-3
3
6
Speed Grade
400
250
100
±50
100
100
±50
4.0
0.0
4.0
0.0
7.5
3.0
0.5
3.0
0.5
8.0
0.5
9.0
7.5
1.0
2.0
10
50
10
60
66
66
-2
3
6
400
250
100
±50
100
100
±50
4.0
0.0
4.0
0.0
7.5
3.0
0.5
3.0
0.5
8.0
0.5
9.0
7.5
1.0
2.0
10
50
10
60
66
66
-1
3
6
ms, Min/Max
MHz, Max
MHz, Max
MHz, Max
MHz, Max
ms, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Units
MHz,
MHz
Max
%
%
51