XC5VSX50T-1FFG665I Xilinx Inc, XC5VSX50T-1FFG665I Datasheet

FPGA Virtex®-5 Family 52224 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA

XC5VSX50T-1FFG665I

Manufacturer Part Number
XC5VSX50T-1FFG665I
Description
FPGA Virtex®-5 Family 52224 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr

Specifications of XC5VSX50T-1FFG665I

Package
665FCBGA
Family Name
Virtex®-5
Device Logic Units
52224
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
360
Ram Bits
4866048
Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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0
XCN07026 (v1.0.3) July 29, 2009
Overview
The purpose of this notification is to communicate a transition to Step 1 and a 10-layer package substrate for select
Virtex®-5 LXT and SXT FPGA devices.
Description
This notification includes the following changes to be implemented:
Key Dates and Ordering Information
Key dates for this notice are detailed in Key Dates for Package Transition.
XCN07026 (v1.0.3) July 29, 2009
Table 1: Key Dates for Package Transition
*
**
If a qualification of the new material is necessary, customers can order samples of Step 1 10-layer devices by appending "S1" to the end of
standard part numbers from January 1, 2008 through April 30, 2008.
Starting from May 1, 2008, orders using standard part numbers will receive devices in either Step 0 or Step 1, 8-layer or 10-layer.
Introduction of Step 1: Specific LXT and SXT devices will begin transitioning to a new mask revision, designated as
Step 1, which will improve the CDM ESD performance. The current production silicon is designated as Step 0. The
Step 1 devices are form, fit, function, and bitstream compatible with Step 0. (For information on the Xilinx Stepping
Methodology, see
Package change: LXT and SXT devices in packages greater than 1000 pins will begin transitioning to 10-layer
package substrates, as part of the Xilinx material standardization for the Virtex-5 FPGA family. This change is
backward-compatible with current production devices. This change will not affect the current package outline drawing.
December 31, 2007
Notification Date
© Copyright 2007 - 2009 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx logo, the Brand Window and other designated brands
Xilinx Answer
included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.
20947).
January 1, 2008 - April 30, 2008
Transition Period*
www.xilinx.com
Transition to Step 1 and New
Package Substrate for Select
Virtex-5 LXT and SXT FPGA
Devices
(Cross-shipping starts)
Implementation Date**
Product/Process Change Notice
May 1, 2008
1

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XC5VSX50T-1FFG665I Summary of contents

Page 1

XCN07026 (v1.0.3) July 29, 2009 Overview The purpose of this notification is to communicate a transition to Step 1 and a 10-layer package substrate for select Virtex®-5 LXT and SXT FPGA devices. Description This notification includes the following changes to ...

Page 2

... XC5VSX50T-FF(G)1136 XC5VSX95T-FF(G)1136 XC5VLX30T-FF(G)665 XC5VLX50T-FF(G)665 Yes XC5VSX50T-FF(G)665 Traceability Step 1 10-layer devices can be ordered by appending "S1" to the end of the standard part number. Standard ordering part numbers may be fulfilled with either 8-layer or 10-layer substrates. The top mark facilitates traceability. Step 1 devices can be visually identified by the additional "1" at the end of the third line of the package top mark (see Example Top Mark) ...

Page 3

Response Note: In accordance with JESD46-C, this change is deemed accepted by the customer if no acknowledgement is received within 30 days from this notice. No response is required by this notice. For additional information or questions, please contact Important ...

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