XC6SLX150T-3FGG676I Xilinx Inc, XC6SLX150T-3FGG676I Datasheet - Page 45

• Manufacturer Part Number: XC6SLX150T-3FGG676I
• Description: FPGA Spartan®-6 Family 147443 Cells 45nm (CMOS) Technology 1.2V 676-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan® 6 LXTr

Specifications of XC6SLX150T-3FGG676I

• Package: 676FBGA
• Family Name: Spartan®-6
• Device Logic Cells: 147443
• Device Logic Units: 92152
• Number Of Registers: 184304
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 396
• Ram Bits: 4939776
• Package / Case: 676-BGA
• Mounting Type: Surface Mount
• Voltage - Supply: 1 V ~ 3.6 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 396
• Number Of Logic Elements/cells: 147443
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 44: Device DNA Interface Port Switching Characteristics
Table 45: Suspend Mode Switching Characteristics
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Notes:
1.
2.
T
T
T
T
T
T
T
T
T
T
Entering Suspend Mode
T
T
T
T
T
Exiting Suspend Mode
T
T
T
T
T
T
T
AWAKE_GWE1
AWAKE_GWE512
AWAKE_GTS1
AWAKE_GTS512
DNASSU
DNASH
DNADSU
DNADH
DNARSU
DNARH
DNADCKO
DNACLKF
DNACLKL
DNACLKH
SUSPENDHIGH_AWAKE
SUSPENDFILTER
SUSPEND_GWE
SUSPEND_GTS
SUSPEND_DISABLE
SUSPENDLOW_AWAKE
SUSPEND_ENABLE
SCP_AWAKE
The minimum READ pulse width is 8 ns, the maximum READ pulse width is 1 µs.
Also applies to TCK when reading DNA through the boundary-scan port.
Symbol
Symbol
(2)
Setup time on SHIFT before the rising edge of CLK
Hold time on SHIFT after the rising edge of CLK
Setup time on DIN before the rising edge of CLK
Hold time on DIN after the rising edge of CLK
Setup time on READ before the rising edge of CLK
Hold time on READ after the rising edge of CLK
Clock-to-output delay on DOUT after rising edge of CLK
CLK frequency
CLK Low time
CLK High time
Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter
Adjustment to SUSPEND pin rising edge parameters when glitch filter enabled
Rising edge of SUSPEND pin until FPGA output pins drive their defined
SUSPEND constraint behavior (without glitch filter)
Rising edge of SUSPEND pin to write-protect lock on all writable clocked
elements (without glitch filter)
Rising edge of the SUSPEND pin to FPGA input pins and interconnect
disabled (without glitch filter)
Falling edge of the SUSPEND pin to rising edge of the AWAKE pin. Does not
include DCM or PLL lock time.
Falling edge of the SUSPEND pin to FPGA input pins and interconnect re-
enabled
Rising edge of the AWAKE pin until write-protect lock released on all writable
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1.
Rising edge of the AWAKE pin until write-protect lock released on all writable
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512.
Rising edge of the AWAKE pin until outputs return to the behavior described in
the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1.
Rising edge of the AWAKE pin until outputs return to the behavior described in
the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:512.
Rising edge of SCP pins to rising edge of AWAKE pin
Description
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Description
-3
Speed Grade
-3N
1,000
0.5
50
50
7
1
1
1
7
7
6
2
-2
Min
2.5
31
–
–
–
7
7
–
–
–
–
7
-1L
1500
Max
20.5
20.5
430
14
15
15
75
41
80
80
75
MHz, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Units
Units
ns
ns
ns
ns
ns
µs
µs
ns
µs
ns
µs
µs
45