XC6VLX75T-2FFG484C Xilinx Inc, XC6VLX75T-2FFG484C Datasheet
XC6VLX75T-2FFG484C
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XC6VLX75T-2FFG484C Summary of contents
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DS150 (v2.2) January 28, 2010 General Description The Virtex®-6 family provides the newest, most advanced features in the FPGA market. Virtex-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to ...
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... Virtex-6 FPGA Feature Summary Table 1: Virtex-6 FPGA Feature Summary by Device Configurable Logic Blocks (CLBs) Logic Device Cells Max (1) Slices Distributed RAM (Kb) XC6VLX75T 74,496 11,640 1,045 XC6VLX130T 128,000 20,000 1,740 XC6VLX195T 199,680 31,200 3,040 XC6VLX240T 241,152 37,680 3,650 XC6VLX365T 364,032 56,880 4,130 ...
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... Virtex-6 LXT and SXT FPGA package combinations with the maximum available I/Os per package are shown in Table 2: Virtex-6 LXT and SXT FPGA Device-Package Combinations and Maximum Available I/Os FF484 Package FFG484 Size (mm Device GTXs I/O XC6VLX75T 8 240 XC6VLX130T 8 240 XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T ...
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Configuration Virtex-6 FPGAs store their customized configuration in SRAM-type internal latches. The number of configuration bits is between 26 Mb and 160 MB), depending on device size but independent of the specific user-design implementation, unless compression ...
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Clock Management Each Virtex-6 FPGA has up to nine clock management tiles (CMTs), each consisting of two mixed-mode clock managers (MMCMs), which are PLL based. Phase-Locked Loop The MMCM can serve as a frequency synthesizer for a wider range of ...
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Block RAM Every Virtex-6 FPGA has between 156 and 1064 dual-port block RAMs, each storing 36 Kbits. Each block RAM has two completely independent ports that share nothing but the stored data. Synchronous Operation Each memory access, read and write, ...
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Input/Output The number of I/O pins varies from 240 to 1200 depending on device and package size. Each I/O pin is configurable and can comply with a large number of standards, using up to 2.5V. The Virtex-6 FPGA SelectIO Resources ...
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The System Monitor does not require explicit instantiation in a design. Once the appropriate power supply connections are made, measurement data can be accessed at any time, even pre-configuration or during power down, through the JTAG test access port (TAP). ...
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This block is highly configurable to system design requirements and can operate lanes at the 2.5 Gb/s data rate and the 5.0 Gb/s data rate. For high-performance applications, advanced buffering techniques of the block offer ...
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Revision History The following table shows the revision history for this document: Date Version 02/02/09 1.0 Initial Xilinx release. 05/05/09 1.1 Added the FF1156 package for both the XC6VSX315T and XC6VSX475T devices in Updated the PCI Express design discussion on ...
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Virtex-6 FPGA Documentation Complete and up-to-date documentation of the Virtex-6 family of FPGAs is available on the Xilinx website. In addition to the most recent Virtex-6 Family Overview, the following files are also available for download: Virtex-6 FPGA Data Sheet: ...