XC6VSX475T-1FF1759I Xilinx Inc, XC6VSX475T-1FF1759I Datasheet
XC6VSX475T-1FF1759I
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XC6VSX475T-1FF1759I Summary of contents
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DS150 (v2.2) January 28, 2010 General Description The Virtex®-6 family provides the newest, most advanced features in the FPGA market. Virtex-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to ...
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... XC6VLX240T 241,152 37,680 3,650 XC6VLX365T 364,032 56,880 4,130 XC6VLX550T 549,888 85,920 6,200 XC6VLX760 758,784 118,560 8,280 XC6VSX315T 314,880 49,200 5,090 XC6VSX475T 476,160 74,400 7,640 XC6VHX250T 251,904 39,360 3,040 XC6VHX255T 253,440 39,600 3,050 XC6VHX380T 382,464 59,760 4,570 XC6VHX565T 566,784 88,560 6,370 Notes: 1 ...
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... XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T Notes: 1. Flip-chip packages are also available in Pb-Free versions (FFG). Virtex-6 HXT FPGA package combinations with the maximum available I/Os per package are shown in Table 3: Virtex-6 HXT FPGA Device-Package Combinations and Maximum Available I/Os FF1154 ...
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Configuration Virtex-6 FPGAs store their customized configuration in SRAM-type internal latches. The number of configuration bits is between 26 Mb and 160 MB), depending on device size but independent of the specific user-design implementation, unless compression ...
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Clock Management Each Virtex-6 FPGA has up to nine clock management tiles (CMTs), each consisting of two mixed-mode clock managers (MMCMs), which are PLL based. Phase-Locked Loop The MMCM can serve as a frequency synthesizer for a wider range of ...
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Block RAM Every Virtex-6 FPGA has between 156 and 1064 dual-port block RAMs, each storing 36 Kbits. Each block RAM has two completely independent ports that share nothing but the stored data. Synchronous Operation Each memory access, read and write, ...
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Input/Output The number of I/O pins varies from 240 to 1200 depending on device and package size. Each I/O pin is configurable and can comply with a large number of standards, using up to 2.5V. The Virtex-6 FPGA SelectIO Resources ...
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The System Monitor does not require explicit instantiation in a design. Once the appropriate power supply connections are made, measurement data can be accessed at any time, even pre-configuration or during power down, through the JTAG test access port (TAP). ...
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This block is highly configurable to system design requirements and can operate lanes at the 2.5 Gb/s data rate and the 5.0 Gb/s data rate. For high-performance applications, advanced buffering techniques of the block offer ...
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... Initial Xilinx release. 05/05/09 1.1 Added the FF1156 package for both the XC6VSX315T and XC6VSX475T devices in Updated the PCI Express design discussion on description and clarify 8 lanes at the 5.0 Gb/s data rate. Clerical edits to 10/100/1000 Mb/s Ethernet Controller (2500 Mb/s Supported) text ...
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Virtex-6 FPGA Documentation Complete and up-to-date documentation of the Virtex-6 family of FPGAs is available on the Xilinx website. In addition to the most recent Virtex-6 Family Overview, the following files are also available for download: Virtex-6 FPGA Data Sheet: ...