XCV50E-6PQ240C Xilinx Inc, XCV50E-6PQ240C Datasheet - Page 3
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XCV50E-6PQ240C
Manufacturer Part Number
XCV50E-6PQ240C
Description
FPGA Virtex™-E Family 20.736K Gates 1728 Cells 357MHz 0.18um (CMOS) Technology 1.8V 240-Pin PQFP
Manufacturer
Xilinx Inc
Series
Virtex™-Er
Specifications of XCV50E-6PQ240C
Package
240PQFP
Family Name
VirtexÂ-E
Device Logic Gates
20736
Device Logic Units
1728
Device System Gates
71693
Maximum Internal Frequency
357 MHz
Typical Operating Supply Voltage
1.8 V
Maximum Number Of User I/os
158
Ram Bits
65536
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
384
Total Ram Bits
65536
Number Of I /o
158
Number Of Gates
71693
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-BFQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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resources. The abundance of routing resources permits the
Virtex-E family to accommodate even the largest and most
complex designs.
Virtex-E FPGAs are SRAM-based, and are customized by
loading configuration data into internal memory cells. Con-
figuration data can be read from an external SPROM (mas-
ter serial mode), or can be written into the FPGA
(SelectMAP™, slave serial, and JTAG modes).
The standard Xilinx Foundation Series™ and Alliance
Series™ Development systems deliver complete design
support for Virtex-E, covering every aspect from behavioral
and schematic entry, through simulation, automatic design
translation and implementation, to the creation and down-
loading of a configuration bit stream.
Higher Performance
Virtex-E devices provide better performance than previous
generations of FPGAs. Designs can achieve synchronous
system clock rates up to 240 MHz including I/O or 622 Mb/s
using Source Synchronous data transmission architech-
tures. Virtex-E I/Os comply fully with 3.3 V PCI specifica-
tions, and interfaces can be implemented that operate at
33 MHz or 66 MHz.
While performance is design-dependent, many designs
operate internally at speeds in excess of 133 MHz and can
achieve over 311 MHz.
representative circuits, using worst-case timing parameters.
Virtex-E Device/Package Combinations and Maximum I/O
Table 3: Virtex-E Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins)
DS022-1 (v2.3) July 17, 2002
Production Product Specification
FG1156
HQ240
CS144
PQ240
BG352
BG432
BG560
FG256
FG456
FG676
FG680
FG860
FG900
R
XCV
50E
158
176
94
100E
Table 2
XCV
158
196
176
94
shows performance data for
200E
XCV
158
260
176
284
94
300E
XCV
158
260
316
176
312
www.xilinx.com
400E
1-800-255-7778
XCV
158
316
404
404
Table 2: Performance for Common Circuit Functions
600E
Register-to-Register
Adder
Pipelined Multiplier
Address Decoder
16:1 Multiplexer
Parity Tree
Chip-to-Chip
HSTL Class IV
LVTTL,16mA, fast slew
LVDS
LVPECL
XCV
158
316
404
444
512
512
Virtex™-E 1.8 V Field Programmable Gate Arrays
Function
1000E
XCV
158
404
512
660
660
660
1600E
XCV
404
512
660
700
724
16 x 16
8 x 8
Bits
16
64
16
64
18
36
9
2000E
XCV
404
512
660
804
2600E
Virtex-E (-7)
XCV
804
4.3 ns
6.3 ns
4.4 ns
5.1 ns
3.8 ns
5.5 ns
4.6 ns
3.5 ns
4.3 ns
5.9 ns
Module 1 of 4
3200E
XCV
804
3