MAX2769ETI+ Maxim Integrated Products, MAX2769ETI+ Datasheet - Page 19

• Manufacturer Part Number: MAX2769ETI+
• Description: RF Receiver Low-Power GPS and GL ONASS Receiver with
• Manufacturer: Maxim Integrated Products

Specifications of MAX2769ETI+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8. Configuration 3 (Address: 0010)
STRMCOUNT
TIMESYNCEN
STRMSTART
DATSYNCEN
STRMSTOP
HILOADEN
STRMBITS
DATA BIT
FSLOWEN
STAMPEN
STRMRST
FOFSTEN
PGAQEN
STRMEN
PGAIEN
GAININ
ADCEN
FHIPEN
DRVEN
FILTEN
—
LOCATION
______________________________________________________________________________________
27:22
8:6
5:4
21
20
19
18
17
16
15
14
13
12
11
10
9
3
2
1
0
DEFAULT
VALUE
111010
111
01
1
0
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
PGA gain value programming from the serial interface in steps of dB per LSB.
Low value of the ADC full-scale enable. Set 1 to enable or 0 to disable.
Set 1 to enable the output driver to drive high loads.
ADC enable. Set 1 to enable ADC or 0 to disable.
Output driver enable. Set 1 to enable the driver or 0 to disable.
Filter DC offset cancellation circuitry enable. Set 1 to enable the circuitry or 0 to
IF filter enable. Set 1 to enable the filter or 0 to disable.
Highpass coupling enable. Set 1 to enable the highpass coupling between the filter
and PGA, or 0 to disable the coupling.
Reserved.
I-channel PGA enable. Set 1 to enable PGA in the I channel or 0 to disable.
Q-channel PGA enable. Set 1 to enable PGA in the Q channel or 0 to disable.
DSP interface for serial streaming of data enable. This bit configures the IC such
that the DSP interface is inserted in the signal path. Set 1 to enable the interface
or 0 to disable the interface.
The positive edge of this command enables data streaming to the output. It also
enables clock, data sync, and frame sync outputs.
The positive edge of this command disables data streaming to the output. It also
disables clock, data sync, and frame sync outputs.
Sets the length of the data counter from 128 (000) to 16,394 (111) bits per frame.
Number of bits streamed. D5:D4 = 00: I MSB; 01: I MSB, I LSB; 10: I MSB, Q MSB;
11: I MSB, I LSB, Q MSB, Q LSB.
The signal enables the insertion of the frame number at the beginning of each
frame. If disabled, only the ADC data is streamed to the output.
This signal enables the output of the time sync pulses at all times when streaming
is enabled by the STRMEN command. Otherwise, the time sync pulses are
available only when data streaming is active at the output, for example, in the time
intervals bound by the STRMSTART and STRMSTOP commands.
This control signal enables the sync pulses at the DATASYNC output. Each pulse
is coincident with the beginning of the 16-bit data word that corresponds to a
given output bit.
This command resets all the counters irrespective of the timing within the
stream cycle.
Universal GPS Receiver
DESCRIPTION
19