MAX7060ATG/V+ Maxim Integrated Products, MAX7060ATG/V+ Datasheet - Page 24

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MAX7060ATG/V+

Manufacturer Part Number
MAX7060ATG/V+
Description
RF Transmitter 300MHz to 450MHz Fre quency-and-Output-Po
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX7060ATG/V+

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
280MHz to 450MHz Programmable
ASK/FSK Transmitter
Table 14. FSK High-Frequency 1 (FHigh1) Register (Address: 0x0A)
The 4 MSBs of FHigh0, fhi[15:12], are the integer portion of the divider, excluding offset of 16. The 12 LSBs (fhi[11:0])
are the fractional part of the divider.
Table 15. ASK Center-Frequency 0 (FCenter0) Register (Address: 0x0B)
Table 16. ASK Center-Frequency 1 (FCenter1) Register (Address: 0x0C)
The 4 MSBs of FCenter0, fce[15:12], are the integer portion of the divider, excluding offset of 16. The 12 LSBs (fce[11:0)
are the fractional part of the divider.
When fce[11:0] are all zeros and ASK mode is selected (mode bit = 0), the PLL works in the fixed-N mode, which
reduces current consumption and reference spurs. Set pllbw bit high (Conf0 register, bit 5). For all other combinations,
the PLL works in fractional-N mode.
Table 17. FSK Low-Frequency 0 (FLow0) Register (Address:0x0D)
Table 18. FSK Low-Frequency 1 (FLow1) Register (Address: 0x0E)
The 4 MSBs of FLow0, flo[15:12], are the integer portion of the divider, excluding offset of 16. The 12 LSBs (flo[11:0])
are the fractional part of the divider.
Table 19. Maximum and Minimum Values for Frequency Divider
Table 20. Frequency-Load (FLoad) Register (Address: 0x0F)
24
BIT
BIT
BIT
BIT
BIT
BIT
7:0
7:0
7:0
7:0
7:0
0
_____________________________________________________________________________________
fce[15:8]
flo[15:8]
fce[7:0]
fhi[7:0]
flo[7:0]
NAME
NAME
NAME
NAME
NAME
NAME
hop
DECIMAL VALUE
8-bit lower byte of high-frequency divider for FSK
8-bit upper byte of frequency divider for ASK
8-bit lower byte of frequency divider for ASK
8-bit upper byte of low-frequency divider for FSK
8-bit lower byte of low-frequency divider for FSK
Effectively changes the PLL frequency to the ones written in registers 0x09 to 0x0E. This is a self-reset bit
and is reset to zero after the operation is completed.
12.0220
2.9536
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
fhi[15:0], fce[15:0], flo[15:0]
0xC05A
0x2F42

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