MC74HC4046AD ON Semiconductor, MC74HC4046AD Datasheet - Page 8

• Manufacturer Part Number: MC74HC4046AD
• Description: Phase Locked Loops (PLL) LOG CMOS PLL
• Manufacturer: ON Semiconductor
• Type: PLLr

Specifications of MC74HC4046AD

• Number Of Circuits: 1
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 55 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Package / Case: SOIC-16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Phase Comparators
COMP
network that enables AC coupling of input signals. If the
signals are not AC coupled, standard 74HC input levels are
required. Both input structures are shown in Figure 7. The
Phase Comparator 1
74HC86. Its operation is similar to an overdriven balanced
modulator. To maximize lock range the input frequencies
must have a 50% duty cycle. Typical input and output
waveforms are shown in Figure 8. The output of the phase
detector feeds the loop filter which averages the output
voltage. The frequency range upon which the PLL will lock
onto if initially out of lock is defined as the capture range.
The capture range for phase detector 1 is dependent on the
loop filter design. The capture range can be as large as the
lock range, which is equal to the VCO frequency range.
two square wave signals are applied to this comparator, an
output waveform (whose duty cycle is dependent on the
phase difference between the two signals) results. As the
phase difference increases, the output duty cycle increases
and the voltage after the loop filter increases. In order to
achieve lock when the PLL input frequency increases, the
VCO input voltage must increase and the phase difference
between COMP
frequency equal to f
requires the phase detector output to be grounded; hence, the
All three phase comparators have two inputs, SIG
This comparator is a simple XOR gate similar to the
To see how the detector operates, refer to Figure 8. When
IN
COMP
SIG
. The SIG
14
3
IN
IN
IN
V
IN
V
and SIG
CC
CC
min
and COMP
, the VCO input is at 0 V. This
IN
will increase. At an input
IN
Figure 7. Logic Diagram for Phase Comparators
have a special DC bias
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MC74HC4046A
IN
and
8
outputs of these comparators are essentially standard 74HC
outputs (comparator 2 is TRI−STATEABLE). In normal
operation V
filter. This differs from some phase detectors which supply
a current to the loop filter and should be considered in the
design. (The MC14046 also provides a voltage).
two input signals must be in phase. When the input
frequency is f
detector inputs must be 180 degrees out of phase.
of the SIG
a signal 2 times the VCO frequency results in the same
output duty cycle as a signal equal to the VCO frequency.
The difference is that the output frequency of the 2f example
is twice that of the other example. The loop filter and VCO
range should be designed to prevent locking on to
harmonics.
COMP
PC1
The XOR is more susceptible to locking onto harmonics
VCO
SIG
OUT
IN
IN
IN
Figure 8. Typical Waveforms for PLL Using
IN
CC
than the digital phase detector 2. For instance,
max
and ground voltage levels are fed to the loop
, the VCO input must be V
Phase Comparator 1
V
CC
PCP
PC2
PC3
PC1
15
13
1
2
CC
OUT
OUT
OUT
OUT
and the phase
V
GND
CC