DLP-HS-FPGA2 DLP Design Inc, DLP-HS-FPGA2 Datasheet - Page 3

• Manufacturer Part Number: DLP-HS-FPGA2
• Description: Interface Modules & Development Tools USB FPGA Module w/ Xilinx XC3S400A
• Manufacturer: DLP Design Inc
• Series: -r

Specifications of DLP-HS-FPGA2

• Interface Type: USB
• Description/function: USB - FPGA Module
• Dimensions: 71.1 mm x 30.5 mm x 5.3 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Channels: 2
• Operating Supply Voltage: 3.6 V to 6 V
• Product: Interface Modules
• Supply Voltage (max): 6 V
• Supply Voltage (min): 3.6 V
• Wireless Frequency: 66 MHz
• Main Purpose: Interface, USB to FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: FT2232D, XC3S400A-4FTG256C
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Xilinx Spartan 3A, FTDI FT2232H Dual-Channel High-Speed USB IC

user-supplied, 0.05-inch spaced, 2x13 connector such as the FFSD-13-D-xx.xx-01 (xx.xx = cable
length) ribbon cable assembly from Samtec.
DIP Socket
Ribbon Cable
Other on-board features include a 32M x 8 DDR2 SDRAM memory IC for user projects and both
JTAG and SPI Flash interface ports for connection to Xilinx programming tools.
2.0 REFERENCE DESIGN
A 10,000-line reference design is available for the Spartan™ 3A FPGA on the DLP-HS-FPGA to those
who purchase the module. The design was written in VHDL and built using the free Xilinx ISE™
WebPACK™ tools. The reference design consists of the following blocks:
It contains a USB Interface Block, a User I/0 Block, a DDR2 SDRAM interface, a Heartbeat Pulse
Generator and a Clock Generator. The SPI Flash is used to store the design’s FPGA configuration
file.
The USB interface captures, interprets and returns command and data information sent from the host
PC through the FTDI USB interface to the FPGA. Commands include Ping, Return Status, Loopback
Data, Set a User I/O Pin High or Low, Read a User I/O Pin, Initialize the DDR2 SDRAM Memory and
Read or Write the DDR2 SDRAM Memory. (Section 11 explains these in detail.)
Rev. 1.3 (March 2011)
3
© DLP Design, Inc.