72240L15TP Integrated Device Technology (Idt), 72240L15TP Datasheet

72240L15TP

Manufacturer Part Number

72240L15TP

Description

FIFO Mem Sync Dual Depth/Width Uni-Dir 4K x 8 28-Pin PDIP

Manufacturer

Integrated Device Technology (Idt)

Datasheet

1.IDT72200L25TP.pdf (11 pages)

Specifications of 72240L15TP

Package

28PDIP

Configuration

Dual

Bus Directional

Uni-Directional

Density

32 Kb

Organization

4Kx8

Data Bus Width

8 Bit

Timing Type

Synchronous

Expansion Type

Depth|Width

Typical Operating Supply Voltage

5 V

Operating Temperature

0 to 70 Â°C

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FEATURES:

• • • • •

FUNCTIONAL BLOCK DIAGRAM

IDT, IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

Green parts available, see ordering information

64 x 8-bit organization (IDT72420)

256 x 8-bit organization (IDT72200)

512 x 8-bit organization (IDT72210)

1,024 x 8-bit organization (IDT72220)

2,048 x 8-bit organization (IDT72230)

4,096 x 8-bit organization (IDT72240)

10 ns read/write cycle time (IDT72420/72200/72210/72220/72230/

72240)

Read and Write Clocks can be asynchronous or coincidental

Dual-Ported zero fall-through time architecture

Empty and Full flags signal FIFO status

Almost-Empty and Almost-Full flags set to Empty+7 and Full-7,

respectively

Output enable puts output data bus in high-impedance state

Produced with advanced submicron CMOS technology

Available in 28-pin 300 mil plastic DIP

For surface mount product please see the IDT72421/72201/72211/

72221/72231/72241 data sheet

Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available

WRITE CONTROL

WRITE POINTER

RESET LOGIC

WCLK

LOGIC

WEN

CMOS SyncFIFO™

64 x 8, 256 x 8,

512 x 8, 1,024 x 8,

2,048 x 8 and 4,096 x 8

OUTPUT REGISTER

2,048 x 8, 4,096 x 8

512 x 8, 1,024 x 8,

INPUT REGISTER

64 x 8, 256 x 8,

RAM ARRAY

D0 - D7

Q0 - Q7

DESCRIPTION:

high-speed, low-power First-In, First-Out (FIFO) memories with clocked

read and write controls. These devices have a 64, 256, 512, 1,024, 2,048,

and 4,096 x 8-bit memory array, respectively. These FIFOs are applicable

for a wide variety of data buffering needs, such as graphics, Local Area

Networks (LANs), and interprocessor communication.

controlled by a free-running clock (WCLK), and a Write Enable pin (WEN).

Data is written into the Synchronous FIFO on every clock when WEN is

asserted. The output port is controlled by another clock pin (RCLK) and a

Read Enable pin (REN). The Read Clock can be tied to the Write Clock for

single clock operation or the two clocks can run asynchronous of one

another for dual clock operation. An Output Enable pin (OE) is provided on

the read port for three-state control of the output.

(FF). Two partial flags, Almost-Empty (AE) and Almost-Full (AF), are

provided for improved system control. The partial (AE) flags are set to

Empty+7 and Full-7 for AE and AF respectively.

technology.

These FIFOs have 8-bit input and output ports. The input port is

These Synchronous FIFOs have two endpoint flags, Empty (EF) and Full

These FIFOs are fabricated using IDT’s high-speed submicron CMOS

The IDT72420/72200/72210/72220/72230/72240 SyncFIFO™ are very

READ CONTROL

READ POINTER

RCLK

LOGIC

FLAG

LOGIC

REN

JANUARY 2009

2680 drw01

IDT72420

IDT72200

IDT72210

IDT72220

IDT72230

IDT72240

DSC-2680/5

Related parts for 72240L15TP

72240L15TP Summary of contents

Page 1

FEATURES: • • • • • 8-bit organization (IDT72420) • • • • • 256 x 8-bit organization (IDT72200) • • • • • 512 x 8-bit organization (IDT72210) • • • • • 1,024 x 8-bit organization ...

Page 2

IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™ 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 PIN CONFIGURATION PIN DESCRIPTIONS Symbol Name I Data Inputs I Data inputs for a 8-bit bus. ...

IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™ 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 ABSOLUTE MAXIMUM RATINGS Symbol Rating Com'l & Ind'l V Terminal Voltage with –0.5 to +7.0 TERM Respect to GND ...

Page 4

IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™ 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 ELECTRICAL CHARACTERISTICS (Commercial ± 10 0° 70° Symbol Parameter ...

Page 5

IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™ 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 SIGNAL DESCRIPTIONS INPUTS: Data In (D –D ) — Data inputs for 8-bit wide data CONTROLS: RESET ...

Page 6

IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™ 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 REN WEN EF NOTES: 1. After reset, the outputs will ...

Page 7

IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™ 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 CLKH RCLK t t ENS ENH REN OLZ OE WCLK WEN ...

Page 8

IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™ 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 WRITE WCLK t SKEW1 WEN RCLK t ENH t ENS REN t ...

Page 9

IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™ 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 CLKH WCLK t ENS WEN AF Full - 8 words in FIFO RCLK REN NOTES: is the minimum ...

Page 10

IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™ 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION - A single IDT72420/72200/72210/ 72220/72230/72240 may be used when the application requirements are for ...

Page 11

DEPTH EXPANSION The IDT72420/72200/72210/72220/72230/72240 can be adapted to applications when the requirements are for greater than 64/256/512/1,024/ 2,048/4,096 words. Depth expansion is possible by using expansion logic to direct the flow of data. A typical application would have the expansion ...

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