72265LA10TF Integrated Device Technology (Idt), 72265LA10TF Datasheet - Page 13

• Manufacturer Part Number: 72265LA10TF
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 18 64-Pin STQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72265LA10TF

• Package: 64STQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 288 Kb
• Organization: 16Kx18
• Data Bus Width: 18 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

WRITE ENABLE (WEN)
array on the rising edge of every WCLK cycle if the device is not full. Data
is stored in the RAM array sequentially and independently of any ongoing
read operation.
WCLK cycle.
inhibiting further write operations. Upon the completion of a valid read cycle,
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles + t
further write operations. Upon the completion of a valid read cycle, IR will
go LOW allowing a write to occur. The IR flag is updated by two WCLK
cycles + t
mode.
READ CLOCK (RCLK)
be read on the outputs, on the rising edge of the RCLK input. It is permis-
sible to stop the RCLK. Note that while RCLK is idle, the EF/OR, PAE and
HF flags will not be updated. (Note that RCLK is only capable of updating
the HF flag to HIGH). The Write and Read Clocks can be independent or
coincident.
READ ENABLE (REN)
output register on the rising edge of every RCLK cycle if the device is not
empty.
and no new data is loaded into the output register. The data outputs Q
maintain the previous data value.
word written to an empty FIFO, must be requested using REN. When the
last word has been read from the FIFO, the Empty Flag (EF) will go LOW,
inhibiting further read operations. REN is ignored when the FIFO is empty.
Once a write is performed, EF will go HIGH allowing a read to occur. The
EF flag is updated by two RCLK cycles + t
goes to the outputs Qn, on the third valid LOW to HIGH transition of RCLK +
t
to access all other words, a read must be executed using REN. The RCLK
LOW to HIGH transition after the last word has been read from the FIFO,
Output Ready (OR) will go HIGH with a true read (RCLK with REN =
LOW), inhibiting further read operations. REN is ignored when the FIFO is
empty.
SERIAL ENABLE (SEN)
offset registers. The serial programming method must be selected during
Master Reset. SEN is always used in conjunction with LD. When these lines
are both LOW, data at the SI input can be loaded into the program register
one bit for each LOW-to-HIGH transition of WCLK. (See Figure 4.)
settings and no offsets are loaded. SEN functions the same way in both IDT
Standard and FWFT modes.
IDT72255LA/72265LA CMOS SuperSync FIFO™
8,192 x 18 and 16,384 x 18
SKEW
When the WEN input is LOW, data may be loaded into the FIFO RAM
When WEN is HIGH, no new data is written in the RAM array on each
To prevent data overflow in the IDT Standard mode, FF will go LOW,
To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting
WEN is ignored when the FIFO is full in either FWFT or IDT Standard
A read cycle is initiated on the rising edge of the RCLK input. Data can
When Read Enable is LOW, data is loaded from the RAM array into the
When the REN input is HIGH, the output register holds the previous data
In the IDT Standard mode, every word accessed at Qn, including the first
In the FWFT mode, the first word written to an empty FIFO automatically
The SEN input is an enable used only for serial programming of the
When SEN is HIGH, the programmable registers retains the previous
after the first write. REN does not need to be asserted LOW. In order
SKEW
SKEW
after the RCLK cycle.
after the valid RCLK cycle.
SKEW
after the valid WCLK cycle.
0
-Q
n
13
OUTPUT ENABLE (OE)
receive data from the output register. When OE is HIGH, the output data
bus (Qn) goes into a high impedance state.
LOAD (LD)
input determines one of two default offset values (127 or 1,023) for the PAE
and PAF flags, along with the method by which these offset registers can be
programmed, parallel or serial. After Master Reset, LD enables write op-
erations to and read operations from the offset registers. Only the offset
loading method currently selected can be used to write to the registers.
Offset registers can be read only in parallel. A LOW on LD during Master
Reset selects a default PAE offset value of 07FH (a threshold 127 words
from the empty boundary), a default PAF offset value of 07FH (a threshold
127 words from the full boundary), and parallel loading of other offset
values. A HIGH on LD during Master Reset selects a default PAE offset
value of 3FFH (a threshold 1,023 words from the empty boundary), a
default PAF offset value of 3FFH (a threshold 1,023 words from the full
boundary), and serial loading of other offset values.
process of the flag offset values PAE and PAF. Pulling LD LOW will begin a
serial loading or parallel load or read of these offset values. See Figure 4,
Programmable Flag Offset Programming Sequence.
OUTPUTS:
FULL FLAG (FF/IR)
function is selected. When the FIFO is full, FF will go LOW, inhibiting further
write operations. When FF is HIGH, the FIFO is not full. If no reads are
performed after a reset (either MRS or PRS), FF will go LOW after D writes
to the FIFO (D = 8,192 for the IDT72255LA and 16,384 for the
IDT72265LA). See Figure 7, Write Cycle and Full Flag Timing (IDT Stan-
dard Mode), for the relevant timing information.
when memory space is available for writing in data. When there is no
longer any free space left, IR goes HIGH, inhibiting further write operations.
If no reads are performed after a reset (either MRS or PRS), IR will go
HIGH after D writes to the FIFO (D = 8,193 for the IDT72255LA and 16,385
for the IDT72265LA) See Figure 9, Write Timing (FWFT Mode), for the
relevant timing information.
also counts the presence of a word in the output register. Thus, in FWFT
mode, the total number of writes necessary to deassert IR is one greater
than needed to assert FF in IDT Standard mode.
are double register-buffered outputs.
EMPTY FLAG (EF/OR)
(EF) function is selected. When the FIFO is empty, EF will go LOW,
inhibiting further read operations. When EF is HIGH, the FIFO is not empty.
See Figure 8, Read Cycle, Empty Flag and First Word Latency Timing
(IDT Standard Mode), for the relevant timing information.
LOW at the same time that the first word written to an empty FIFO appears
valid on the outputs. OR stays LOW after the RCLK LOW to HIGH transition
When Output Enable is enabled (LOW), the parallel output buffers
This is a dual purpose pin. During Master Reset, the state of the LD
After Master Reset, the LD pin is used to activate the programming
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF)
In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW
The IR status not only measures the contents of the FIFO memory, but
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag
In FWFT mode, the Output Ready (OR) function is selected. OR goes
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JANUARY 13, 2009