72401L10P Integrated Device Technology (Idt), 72401L10P Datasheet - Page 6

• Manufacturer Part Number: 72401L10P
• Description: FIFO Mem Async Dual Depth/Width Uni-Dir 64 x 4 16-Pin PDIP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72401L10P

• Package: 16PDIP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 256 Bit
• Organization: 64x4
• Data Bus Width: 4 Bit
• Timing Type: Asynchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

NOTES:
1. FIFO is initially full.
2. SO pulse is applied.
3. SI is held HIGH.
4. As soon as IR becomes HIGH the Input Data is loaded into the FIFO.
5. The write pointer is incremented. SI should not go LOW until (t
OUTPUT DATA
NOTES:
1. This data is loaded consecutively A, B, C.
2. Data is shifted out when SO makes a HIGH to LOW transition.
OUTPUT DATA
NOTES:
1. OR HIGH indicates that data is available and a SO pulse may be applied.
2. SO goes HIGH causing the next step.
3. OR goes LOW.
4. The read pointer is incremented.
5. OR goes HIGH indicating that new data (B) is now available at the FIFO outputs.
6. If the FIFO has only one word loaded (A DATA) then OR stays LOW and the A DATA remains unchanged at the outputs.
7. SO pulses applied when OR is LOW will be ignored.
INPUT DATA
IDT72401/72403
CMOS PARALLEL FIFO 64 x 4, 64 x 5
SO
IR
SI
OR
SO
OR
SO
(7)
(1)
(1)
(2)
A-DATA
(1)
Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH
(2)
t
SOH
t
ODH
Figure 6. The Mechanism of Shifting Data Out of the FIFO
(3)
1/f
A- DATA
OUT
PT
+ t
t
IPH
ODS
Figure 5. Output TIming
t
(3)
).
SOL
t
PT
6
B-DATA
t
SIR
t
ORL
(4)
(2)
(4)
1/f
OUT
STABLE DATA
A or B
t
ORH
t
IPH
t
HIR
MILITARY AND COMMERCIAL
TEMPERATURE RANGES
(5)
C-DATA
B- DATA
(6)
(5)
2747 drw 08
2747 drw 09
2747 drw 10