72V205L15PFI Integrated Device Technology (Idt), 72V205L15PFI Datasheet - Page 8

• Manufacturer Part Number: 72V205L15PFI
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 256 x 18 64-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72V205L15PFI

• Package: 64TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 4.5 Kb
• Organization: 256x18
• Data Bus Width: 18 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: -40 to 85 °C

TABLE 3 — TRUTH TABLE FOR CONFIGURATION AT RESET
TABLE 4 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — IDT STANDARD
MODE
TABLE 5 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — FWFT MODE
NOTES:
1. In a daisy-chain depth expansion, FL is held LOW for the "first load device". The RXI and WXI inputs are driven by the corresponding RXO and WXO outputs of the
2. In a daisy-chain depth expansion, FL is held HIGH for members of the expansion other than the "first load device". The RXI and WXI inputs are driven by the corresponding
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
preceding device.
RXO and WXO outputs of the preceding device.
FL
0
1
Output Ready (OR)
0
0
0
1
1
1
(1)
(2)
Buffered Output
Empty Flag (EF)
Double
Double
Single
Single
Triple
Triple
RXI
0
0
1
1
0
0
1
1
WXI
0
1
0
1
0
1
0
1
Single register-buffered
Empty Flag
Triple register-buffered
Output Ready Flag
Double register-buffered
Empty Flag
Single register-buffered
Empty Flag
Single register-buffered
Empty Flag
Triple register-buffered
Output Ready Flag
Double register-buffered
Empty Flag
Single register-buffered
Empty Flag
Buffered Output
Input Ready (IR)
Full Flag (FF)
Double
Double
Double
Double
Single
Single
EF/OR
Timing Mode
Partial Flags
Partial Flags
Single register-buffered
Double register-buffered
Input Ready Flag
Double register-buffered
Single register-buffered
Single register-buffered
Double register-buffered
Input Ready Flag
Double register-buffered
Single register-buffered
Full Flag
Full Flag
Full Flag
Full Flag
Full Flag
Full Flag
Asynch
Synch
Asynch
Asynch
Sync
Sync
8
FF/IR
TM
FL
FL
0
1
0
1
0
1
Programming at Reset
Programming at Reset
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Asynchronous
RXI
RXI
0
0
1
1
0
0
PAE, PAF
WXI
WXI
COMMERCIAL AND INDUSTRIAL
0
1
1
0
0
0
TEMPERATURE RANGES
FIFO Timing Mode
OCTOBER 22, 2008
Figure 24, 26
Figure 24, 26
Flag Timing
Flag Timing
Figure 9, 10
Figure 9, 10
Figure 20, 21
Standard
Standard
Standard
Standard
Standard
Standard
Diagrams
Diagrams
Figure 27
FWFT
FWFT