XC2C32A-6VQG44C Xilinx Inc, XC2C32A-6VQG44C Datasheet - Page 8
![CPLD CoolRunner™-II Family 750 Gates 32 Macro Cells 200MHz 0.18um (CMOS) Technology 1.8V 44-Pin VTQFP](/photos/6/70/67074/xc2c32a-6vqg44c_sml.jpg)
XC2C32A-6VQG44C
Manufacturer Part Number
XC2C32A-6VQG44C
Description
CPLD CoolRunner™-II Family 750 Gates 32 Macro Cells 200MHz 0.18um (CMOS) Technology 1.8V 44-Pin VTQFP
Manufacturer
Xilinx Inc
Series
CoolRunner IIr
Specifications of XC2C32A-6VQG44C
Package
44VTQFP
Family Name
CoolRunnerÂ-II
Device System Gates
750
Number Of Macro Cells
32
Maximum Propagation Delay Time
6 ns
Number Of User I/os
33
Number Of Logic Blocks/elements
2
Typical Operating Supply Voltage
1.8 V
Maximum Operating Frequency
200 MHz
Number Of Product Terms Per Macro
40
Operating Temperature
0 to 70 °C
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.5ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Logic Elements/blocks
2
Number Of Macrocells
32
Number Of Gates
750
Number Of I /o
33
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Features
Programmable
Voltage
1.8V
Memory Type
CMOS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1404
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2C32A-6VQG44C
Manufacturer:
XILINX
Quantity:
5 530
Company:
Part Number:
XC2C32A-6VQG44C
Manufacturer:
XILINX
Quantity:
6 250
Company:
Part Number:
XC2C32A-6VQG44C
Manufacturer:
XilinxInc
Quantity:
3 000
Part Number:
XC2C32A-6VQG44C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Part Number:
XC2C32A-6VQG44C-B100
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
CoolRunner-II CPLD Family
nally generated DataGATE control logic can be assigned to
this I/O pin with the BUFG=DATA_GATE attribute.
Global Signals
Global signals, clocks (GCK), sets/resets (GSR), and output
enables (GTS), are designed to strongly resemble each
other. This approach enables design software to make the
best utilization of their capabilities. Each global capability is
supplemented by a corresponding product term version.
Figure 7
trees. The pin input is buffered, then drives multiple internal
global signal traces to deliver low skew and reduce loading
delays. GCK, GSR, and GTS can also be used as general
8
shows the common structure of the global signal
Figure 6: DataGATE Architecture (output drivers not shown)
Latch
Latch
To AIM
To AIM
MC16
MC16
MC1
MC2
MC1
MC2
PLA
PLA
DataGATE Assertion Rail
www.xilinx.com
AIM
purpose I/Os if they are not needed as global signals. The
DataGATE assertion rail is also a global signal.
Figure 7: Global Clocks (GCK), Sets/Resets (GSR), and
PLA
PLA
MC16
MC16
MC1
MC2
MC1
MC2
Output Enables (GTS)
To AIM
To AIM
To AIM
DS090 (v3.1) September 11, 2008
Latch
Latch
Latch
DS090_07_101001
Product Specification
DS090_06_111201
R