LFXP3C-3TN100C LATTICE SEMICONDUCTOR, LFXP3C-3TN100C Datasheet - Page 22
LFXP3C-3TN100C
Manufacturer Part Number
LFXP3C-3TN100C
Description
FPGA LatticeXP Family 3000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 100-Pin TQFP Tray
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LFXP3C-3QN208C.pdf
(130 pages)
Specifications of LFXP3C-3TN100C
Package
100TQFP
Family Name
LatticeXP
Device Logic Units
3000
Maximum Internal Frequency
320 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
62
Ram Bits
55296
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Price
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Lattice Semiconductor
Figure 2-23. Output Register Block
Figure 2-24. ODDRXB Primitive
Tristate Register Block
The tristate register block provides the ability to register tri-state control signals from the core of the device before
they are passed to the sysIO buffers. The block contains a register for SDR operation and an additional latch for
DDR operation. Figure 2-25 shows the diagram of the Tristate Register Block.
In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D-
type or latch. In DDR mode, ONEG1 is fed into one register on the positive edge of the clock and OPOS1 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
Routing
From
ONEG0
OPOS0
CLK1
*Latch is transparent when input is low.
CLK
LSR
DA
DB
/LATCH
D
D
D-Type
LATCH
LE*
ODDRXB
2-19
Q
Q
Q
0
1
Programmed
Control
LatticeXP Family Data Sheet
OUTDDN
0
1
To sysIO
Buffer
DO
Architecture
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