XC2V1500-5FG676C Xilinx Inc, XC2V1500-5FG676C Datasheet - Page 52

• Manufacturer Part Number: XC2V1500-5FG676C
• Description: FPGA Virtex-II™ Family 1.5M Gates 17280 Cells 750MHz 0.15um/0.12um (CMOS) Technology 1.5V 676-Pin FBGA
• Manufacturer: Xilinx Inc

Specifications of XC2V1500-5FG676C

• Package: 676FBGA
• Family Name: Virtex-II™
• Device Logic Units: 17280
• Device System Gates: 1500000
• Number Of Registers: 15360
• Maximum Internal Frequency: 750 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 392
• Ram Bits: 884736

Table 5: Minimum Power On Current Required for Virtex-II Devices
General Power Supply Requirements
Proper decoupling of all FPGA power supplies is sessential.
Consult Xilinx Application Note
mation on power distribution system design.
V
V
Changes in V
should take place at a rate no faster than 10 mV per milli-
second. Techniques to help reduce jitter and period distor-
DC Input and Output Levels
Values for V
Values for I
mended operating conditions at the V
points. Only selected standards are tested. These are cho-
Table 6: DC Input and Output Levels
DS031-3 (v3.5) November 5, 2007
Product Specification
Notes:
1. Values specified for power on current parameters are Commercial Grade. For Industrial Grade values, multiply Commercial Grade
2. I
I
I
I
CCAUX
CCAUX
CCINTMIN
CCAUXMIN
CCOMIN
Input/Output
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
values by 1.25.
Standard
CCOMIN
LVTTL
PCI33_3
PCI66_3
HSTL IV
HSTL III
HSTL II
HSTL I
PCI–X
GTLP
GTL
is especially susceptible to power supply noise.
powers critical resources in the FPGA. Thus,
(1)
values listed here apply to the entire device (all banks).
R
OL
IL
XC2V250, XC2V500
CCAUX
XC2V40, XC2V80,
and V
and I
V, Min
voltage outside of 200 mV peak to peak
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
200
100
50
OH
IH
are recommended input voltages.
are guaranteed over the recom-
V
V
V
V
V
V
V
35% V
35% V
30% V
30% V
IL
REF
XAPP623
V, Max
REF
REF
REF
REF
REF
Note 2
0.8
0.8
0.7
XC2V1000
– 0.05
– 0.1
– 0.1
– 0.1
– 0.1
– 0.1
CCO
CCO
CCO
CCO
250
100
50
OL
for detailed infor-
and V
V
65% V
65% V
50% V
50% V
V
V
V
V
V
REF
REF
REF
REF
REF
REF
V, Min
Note 2
XC2V1500
2.0
2.0
1.7
+ 0.05
+ 0.1
+ 0.1
+ 0.1
+ 0.1
+ 0.1
350
100
100
OH
CCO
CCO
CCO
CCO
www.xilinx.com
test
V
IH
Virtex-II Platform FPGAs: DC and Switching Characteristics
V
V
V
V
V
V
V
V
XC2V2000
CCO
CCO
CCO
CCO
CCO
CCO
CCO
CCO
V, Max
Device (mA)
Note 2
1.95
tion are provided in Xilinx Answer Record 13756, available
at
V
V
switching output (SSO) limits are essential for keeping
power supply noise to a minimum. Refer to
aging Ground Bounce in Large FPGAs,” to determine the
number of simultaneously switching outputs allowed per
bank at the package level.
sen to ensure that all standards meet their specifications.
The selected standards are tested at minimum V
the respective V
standards are sample tested.
3.6
3.6
2.7
1.7
400
100
100
CCAUX
CCO
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
www.support.xilinx.com
does not have excessive noise. Using simultaneously
can share a power plane with 3.3V V
XC2V3000
10% V
10% V
V, Max
Note 2
500
100
100
V
0.4
0.4
0.4
0.4
0.4
0.6
0.4
0.4
0.4
0.4
0.4
OL
CCO
CCO
OL
and V
XC2V4000
V
V
V
V
V
V
650
100
100
V
V
90% V
90% V
OH
CCO
CCO
CCO
CCO
CCO
CCO
.
CCO
CCO
V, Min
Note 2
V
2.4
n/a
n/a
OH
voltage levels shown. Other
– 0.4
– 0.4
– 0.4
– 0.4
– 0.4
– 0.4
– 0.4
– 0.4
CCO
CCO
XC2V6000
800
100
100
Note 2
Note 2
Note 2
mA
I
24
24
24
16
16
36
40
16
24
48
OL
XAPP689
8
CCO
Module 3 of 4
XC2V8000
, but only if
CCO
1100
Note 2
Note 2
Note 2
100
100
, “Man-
– 24
– 16
mA
– 24
– 24
– 16
– 16
I
n/a
n/a
– 8
– 8
– 8
OH
with
4