XC3S250E-4FT256C Xilinx Inc, XC3S250E-4FT256C Datasheet - Page 107
XC3S250E-4FT256C
Manufacturer Part Number
XC3S250E-4FT256C
Description
FPGA Spartan®-3E Family 250K Gates 5508 Cells 572MHz 90nm (CMOS) Technology 1.2V 256-Pin FTBGA
Manufacturer
Xilinx Inc
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S250E-4FT256C
Package
256FTBGA
Family Name
Spartan®-3E
Device Logic Cells
5508
Device Logic Units
612
Device System Gates
250000
Number Of Registers
4896
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
172
Ram Bits
221184
Available stocks
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Manufacturer
Quantity
Price
Part Number:
XC3S250E-4FT256C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
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Start-Up
At the end of configuration, the FPGA automatically pulses
the Global Set/Reset (GSR) signal, placing all flip-flops in a
known state. After configuration completes, the FPGA
switches over to the user application loaded into the FPGA.
The sequence and timing of how the FPGA switches over is
programmable as is the clock source controlling the
sequence.
The default start-up sequence appears in
the Global Three-State signal (GTS) is released one clock
cycle after DONE goes High. This sequence allows the
DONE signal to enable or disable any external logic used
during configuration before the user application in the FPGA
starts driving output signals. One clock cycle later, the Glo-
bal Write Enable (GWE) signal is released. This allows sig-
nals to propagate within the FPGA before any clocked
storage elements such as flip-flops and block ROM are
enabled.
The function of the dual-purpose I/O pins
VS[2:0], HSWAP, and A[23:0]
DONE pin goes High. When DONE is High, these pins
become user I/Os. Like all user-I/O pins, GTS controls when
the dual-purpose pins can drive out.
DS312-2 (v3.8) August 26, 2009
Product Specification
R
,
also changes when the
,
Figure
such as M[2:0],
69, where
www.xilinx.com
The relative timing of configuration events is programmed
via the Bitstream Generator (BitGen) options in the Xilinx
development software. For example, the GTS and GWE
events can be programmed to wait for all the DONE pins to
High on all the devices in a multiple-FPGA daisy-chain, forc-
ing the FPGAs to start synchronously. Similarly, the start-up
sequence can be paused at any stage, waiting for selected
DCMs to lock to their respective input clock signals. See
also
By default, the start-up sequence is synchronized to CCLK.
Alternatively, the start-up sequence can be synchronized to
a user-specified clock from within the FPGA application
using the STARTUP_SPARTAN3E library primitive and by
setting the
FPGA application can optionally assert the GSR and GTS
signals via the STARTUP_SPARTAN3E primitive. For JTAG
configuration, the start-up sequence can be synchronized
to the TCK clock input.
Stabilizing DCM Clocks Before User
Start-Up Clock
Start-Up Clock
Figure 69: Default Start-Up Sequence
DONE
DONE
Phase
Phase
StartupClk
GWE
GWE
GTS
GTS
DONE High
0
0
bitstream generator option. The
1
1
Default Cycles
Sync-to-DONE
2
2
3
3
Functional Description
4
4
5
5
DS312-2_60_022305
Mode.
6 7
6 7
107
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