XC5VLX50-2FF676I Xilinx Inc, XC5VLX50-2FF676I Datasheet - Page 166
![FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50-2FF676I
Manufacturer Part Number
XC5VLX50-2FF676I
Description
FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-2FF676I
Package
676FCBGA
Family Name
Virtex®-5
Device Logic Units
46080
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
440
Ram Bits
1769472
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
1769472
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF676-500-G - BOARD DEV VIRTEX 5 FF676HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Chapter 4: Block RAM
166
Standard ECC
ECC Encode-Only
Set by Attributes
EN_ECC_READ = TRUE
EN_ECC_WRITE = TRUE
Standard ECC Write
At time T1W, DI[63:0] = A is written into memory location a. The corresponding 8 bits of
ECC parity PA (hex) are generated internally, appended to the 64 data bits, and written into
the memory. Immediately after the write, the parity value PA appears at output
ECCPARITY[7:0]. Since ECC parity is generated internally, DIP[7:0] pins are not used.
Similarly, at time T2W and T3W, DI[63:0] = B and C, together with their corresponding
parity bits PB (hex) and PC (hex) are written into memory locations b and c. PB and PC
appear at output ECCPARITY[7:0] shortly after T2W and T3W.
Standard ECC Read
At time T1R, the 72-bit memory content, consisting 64 bits of data A and 8 bits of parity PA
(hex), of address location a is read and decoded internally. If there is no error, the original
data and parity are output at DO[63:0] and DOP[7:0]. If there is a single-bit error in either
the data or the parity, the error is corrected, and SBITERR is High. If there is a double-bit
error in the data and parity, the error is not corrected. The original data and parity is output
and DBITERR is High.
If attribute DO_REG is set to 0, DO[63:0] = A and DOP[7:0] = PA shortly after T1R.
Similarly, at time T2R and T3R, the memory content at address locations b and c are read
and decoded at DO[63:0] and DOP[7:0]. SBITERR/DBITERR outputs can also switch after
T1R if a single or double-bit error is detected on dataset A.
error (SBITERR) being detected on data A in latch mode after clock edge T1R and a double-
bit error (DBITERR) being detected on data B in latch mode after clock edge T2R.
If attribute DO_REG is set to 1, DO[63:0] = A and DOP[7:0] = PA shortly after T2R.
Similarly, at time T3R and T4R, the memory content at address locations b and c are read
and decoded at DO[63:0] and DOP[7:0]. SBITERR/DBITERR outputs may also switch after
T2R if a single or double-bit error is detected on dataset A.
error (SBITERR) being detected on data A in register mode after clock edge T2R and a
double-bit error (DBITERR) being detected on data B in register mode after clock edge T3R.
In ECC mode, the encode-only port and the decode-only port operate independently of
each other.
Set by Attributes
EN_ECC_READ = FALSE
EN_ECC_WRITE = TRUE
ECC Encode-Only Write
At time T1W, DI[63:0] = A is written into memory location a. The corresponding 8 bits of
ECC parity PA (hex) are generated internally, appended to the 64 data bits, and written into
the memory. Immediately after the write, the parity value PA appears at output
ECCPARITY[7:0]. Since ECC parity is generated internally, DIP[7:0] pins are not used.
www.xilinx.com
Figure 4-32
Figure 4-32
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
shows a single-bit
shows a single-bit
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