XC5VLX50T-1FF665C Xilinx Inc, XC5VLX50T-1FF665C Datasheet - Page 58
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XC5VLX50T-1FF665C
Manufacturer Part Number
XC5VLX50T-1FF665C
Description
FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50T-1FF665C
Package
665FCBGA
Family Name
Virtex®-5
Device Logic Units
46080
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
360
Ram Bits
2211840
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50T-1FF665C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 77: Operating Frequency Ranges for DCM in Maximum Range (MR) Mode
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
3.
4.
Outputs Clocks (Low Frequency Mode)
F
F
F
F
F
F
F
F
Input Clocks (Low Frequency Mode)
F
F
F
F
F
F
1XMRMIN
1XMRMAX
2XMRMIN
2XMRMAX
DLLMRMIN
DLLMRMAX
FXMRMIN
FXMRMAX
CLKINDLLMRMIN
CLKINDLLMRMAX
CLKINFXMRMIN
CLKINFXMRMAX
PSCLKMRMIN
PSCLKMRMAX
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum input
frequency.
When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55
to 55/45).
Symbol
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
CLKIN (using DLL outputs)
CLKIN (using DFS outputs only)
PSCLK
www.xilinx.com
Description
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
(1, 3, 4)
(2, 3, 4)
300.00
19.00
32.00
38.00
64.00
21.34
19.00
40.00
19.00
32.00
40.00
1.19
1.00
1.00
-3
Speed Grade
270.00
38.00
19.00
19.00
32.00
64.00
21.34
40.00
19.00
32.00
40.00
1.19
1.00
1.00
-2
240.00
19.00
32.00
38.00
64.00
21.34
19.00
40.00
19.00
32.00
40.00
1.19
1.00
1.00
-1
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
KHz
58