UPD4990AG Renesas Electronics America, UPD4990AG Datasheet - Page 9

• Manufacturer Part Number: UPD4990AG
• Manufacturer: Renesas Electronics America

Specifications of UPD4990AG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Command input
(1) 3-bit binary code input: C
(2) 4-bit serial transfer command input: C
Number of commands
Commands (C
(1) Register control
The 40-bit shift register is held. The year function is ineffective.
[C
The 40-bit shift register data can be shifted. The year function is ineffective.
[C
Data is transferred from the 40-bit shift register to the time counter. The year function is ineffective.
[C
Data is transferred from the time-counter to the 40-bit shift register. The year function is ineffective.
[C
Register Hold Mode
[C
The 48-bit shift register is held.
The command register is not held.
* The DATA OUT output frequency is 1 Hz.
Register Shift Mode
[C
Data in 52-bit shift registers (including command registers) can be shifted. For command register, data can
be always shifted using the serial command transfer mode.
* The DATA OUT output is LSB data from the shift register.
Time Set and Counter Hold Mode
[C
Data is transferred from the 48-bit shift register to the time counter.
* This command is used to reset the last 10-15 of 15 Stage Binary Divider and holds the time counter.
Time Read Mode
[C
Data is transferred from the time counter to the 48-bit shift register.
* The DATA OUT pin output is a 1 Hz frequency.
15 Stage Binary Divider resetting and time counter release are executed by the following:
The time setting accuracy is 15.625 ms.
The DATA OUT pin outputs LSB data (0 or 1) from the shift register.
After this command is executed, the 40-/48-bit shift register is held and data cannot be shifted.
After this command is executed, the 40-/48-bit shift register is held and data cannot be shifted.
2
3
2
3
2
3
2
3
, C
', C
, C
', C
, C
', C
, C
', C
[C2, C1, C0] = [0, 0, 0] [0, 0, 1] [0, 1, 1] [C3', C2', C1', C0'] = [0, 0, 0, 0] [0, 0, 0, 1] [0, 0, 1, 1]
1
1
1
1
2
2
2
2
, C
, C
, C
, C
', C
', C
', C
', C
3
', C
0
0
0
0
]
1
]
1
]
1
]
1
', C
', C
', C
', C
2
', C
0
0
0
0
']
']
']
']
1
', C
Register control
TP select
TP control
Test mode set
[C
0
' commands are made effective only when [C
2
2
, C
, C
[0, 1, 1] / [0, 0, 1, 1]
1
1
, C
[0, 0, 0] / [0, 0, 0, 0]
[0, 0, 1] / [0, 0, 0, 1]
, C
0
0
] / [C
3
3
', C
', C
2
2
', C
', C
C
[0, 1, 0] / [0, 0, 1, 0]
2
, C
1
1
', C
4
3
0
1
', C
1
, C
0
0
'
0
']
C'
3
, C'
2
, C'
4
8
3
1
2
, C
1
, C'
1
, C
0
0
] = [1, 1, 1].)
PD4990A
7