UPD4991AGS Renesas Electronics America, UPD4991AGS Datasheet
UPD4991AGS
Specifications of UPD4991AGS
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UPD4991AGS Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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User’s Manual PD4991A 4-bit Parallel I/O Calendar Clock Document No. S12923EJ2V0UM00 (2nd edition) Date Published November 1997 N © 1992 Printed in Japan ...
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No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC ...
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CHAPTER 1 OUTLINE OF PD4991A ............................................................................................. 1.1 Features ................................................................................................................................ 1.2 Pin Configuration ................................................................................................................ 1.3 Block Diagram ..................................................................................................................... 1.4 Oscillation Stage and 15-stage Divider ........................................................................... 1.5 Mode and Register Configuration .................................................................................... 1.6 Cautions (Be sure to observe the following.) ................................................................. CHAPTER ...
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APPENDIX ........................................................................................................................................... Appendix 1. Specifications of PD4991A ...................................................................................... Appendix 2. Package Drawing ........................................................................................................ Appendix 3. Differences between PD4991 and PD4991A ....................................................... Caution The application circuits and their parameters are for reference only and are not intended for use in actual ...
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CHAPTER 1 OUTLINE OF PD4991A The PD4991A for inputting/outputting 4-bit parallel time data and calendar data in a microcontroller system and has 1 channel for an alarm function. This IC has seven types of internal counters: year, ...
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Pin Configuration The PD4991A is available in two packages: 18-pin DIP and 20-pin SOP. Figure 1-1 shows the pin configuration. Ordering information is given below. Table 1-1 lists the function of each pin. Ordering information Part Number PD4991ACX 18-pin ...
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CHAPTER 1 OUTLINE OF PD4991A Pin Name Symbol Pin No. DIP Chip select Timing pulse 1 TP1 2 Timing pulse 2 TP2 3 Address input ...
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Block Diagram Figure 1-2 shows the block diagram of the PD4991A. 15-stage OSC Binary Divider OUT ...
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Oscillation Stage and 15-stage Divider A clock of 32.768 kHz is generated by using a 32.768-kHz crystal resonator and a CMOS inverter crystal oscillation circuit. This clock is divided create second) time ...
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Table 1-2. Registers and Their Addresses ADDRESS BASIC TIME MODE HEX MSB LSB (TIME COUNTER Second, units digit Second, tens digit H 2 ...
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Cautions (Be sure to observe the following.) 1. Before writing the time, be sure to stop the watch. For details, refer to 3.1.1 Setting time the 12-hour mode has been changed to the 24-hour mode or vice ...
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Write Timing Address A through A and data “L” and CS = “H” (chip select status takes precedence over OE (read enable). Therefore, data can be written by asserting WE only ...
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Figure 2-2. Write Cycle Timing 2 ( ADDRESS OUT CHAPTER 2 OPERATIONS WHZ ...
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Read Timing The contents of address A through “L” and CS = “H” (chip select status Figures 2-3 and 2-4 show the read timing. When a write-only (W/O) register is read, 0F Because ...
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Mode Details The registers assigned to addresses 0 written to address The PD4991A has the following four major modes. (1) BASIC TIME MODE (MODE REG. In this mode, the timer counter can be accessed. Usually, this ...
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BASIC TIME MODE (MODE REG. In this mode, addresses 0 through Table 2-2). Because a leap year cannot be identified or set and the 12- or 24-hour mode cannot be selected in this mode, setting related ...
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Table 2-2. Register Assignment in BASIC TIME MODE Address Register 0 Second, units digit Directly connected to time counter and updated in real-time. H Data format is BCD. 1 Second, tens digit H If time that does not exist is ...
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Time counter (addresses 0 through 0C H This counter stores time data in BCD format. If time that does not exist is set, the wrong time is indicated. Be sure to set correct data. The day counter takes a ...
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CONTROL REGISTER 1 (address: 0D This register controls clock supply to the timer counter, makes adjustments of 30 seconds, and resets the 15-stage divider. Figure 2-6 shows the configuration of the control register 1, and Table 2-5 shows the ...
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CLOCK STOP and CLOCK WAIT (stops time counter) Both these commands disable input of the clock (1 Hz) to the watch counter and stop the watch. CLOCK STOP is used when time data is written (be sure to stop ...
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Interval timer control block Clock Interval counter Time counter Repeat/1 shot Table 2-6. CONTROL REGISTER 2 Command List (W/ (a) TP1 control (when TP1 DISABLE ( This bit controls ...
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TP2 control (when TP2 DISABLE ( This bit controls output of TP2. When this bit is set, TP2 is forcibly turned off (high impedance) regardless of the other operations. ii) INTERVAL RESET ...
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ALARM SET & TP1 CONTROL MODE (MODE REG. In this mode, addresses 0 through 0A H Address 0B is used as a control register that selects an alarm coincidence signal to be output to TP1, and address H 0C ...
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Example 1. Alarm coincides with the value of the time counter for 10 seconds every hour Month, Month, Date, Date, tens digit units digit tens digit units digit week digit tens digit units digit tens digit units digit tens digit ...
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BUSY signal This is the count flag of the time counter. A carry occurs in the time counter 457.7 s after the BUSY signal has risen. If the value of the time counter is read while a carry occurs, ...
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With auto reset 2048 Alarm coincidence 30 pulse Alarm Alarm coincidence coincidence again "H" "L" Alarm Alarm coincidence non-coinci- dence (3) Leap year counter (low-order 2 bits of address 0C This counter takes a value ...
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ALARM SET & TP2 CONTROL MODE (MODE REG. In this mode, addresses 0 through 0A H MODE). Address 0B is used as a control register that selects an interval signal to be output to TP2, and address H 0C ...
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Table 2-11. TP2 FUNCTION CONTROL REGISTER DATA Operation HEX 0.1 sec INTERVAL sec INTERVAL ...
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Figure 2-11. Interval Signal Output Example TP REPEAT Output status ENABLE RESET START INTERVAL STOP START RESET START INTERVAL STOP 30 Pulse T INTERVAL FLAG ON Note If the output status is disabled, the output ...
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This bit selects the 12-hour mode when when the 24-hour mode is selected. In the 12-hour mode, the second highest bit (D Example Hour, tens digit a.m. ...
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Value Set to Mode Register Operation Mode HEX TEST H (BASIC TIME TEST H (BASIC TIME TEST ...
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Value Set to Mode Register Operation Mode HEX TEST H (ALARM SET & TP2 CONTROL TEST H (ALARM SET & TP1 CONTROL) ...
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CHAPTER 3 ACCESS PROCEDURE 3.1 Writing and Reading Time 3.1.1 Setting time Because the time counter is updated in real-time, the wrong value may be written carry occurs while data is being written to the time ...
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CLK RESET START BASIC TIME MODE No CLK RESET START Notes 1. Once the 12- or 24-hour mode and leap year identification function have been selected, they do not have to be set again. 2. The user does not have ...
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Reading time Because the time counter is updated every second, the wrong time data may be read if the time counter is read when a carry occurs. In principle, the time counter can be read in the following three ...
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Figure 3-3. Reading Time by Using BUSY Signal for Interrupt Main routine Processing 1 Interrupt every second Processing 2 40 CHAPTER 3 ACCESS PROCEDURE Time reading routine Access to PD4991A BASIC TIME MODE, addresses 0 through 0C H ...
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CHAPTER 3 ACCESS PROCEDURE (2) Polling BUSY FLAG In addition to outputting the BUSY signal to TP1 or TP2 as an interrupt signal, the time data can also be read by polling a high-order bit ( the CONTROL ...
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Using CLK WAIT/CLK START command By using the CLK control command of the CONTROL REGISTER 1, disable the carry from occurring while the time data is read. Time is not delayed if the CLK START command is issued within ...
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CHAPTER 3 ACCESS PROCEDURE (4) Reading two times Read the time data two times. If the two values coincide, take that value as the correct value. This procedure is shown in Figure 3-6. Figure 3-6. Reading Time Two Times No ...
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Setting Alarm Time The alarm register can be rewritten at any time because it is independent of the time counter. Figure 3-7 shows the procedure for rewriting the alarm register. Select ALARM SET & TP1 CONT. MODE TP1 output ...
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Setting Interval Timer Because the interval timer is independent of the time counter, it can be stopped, resumed, or reset irrespective of the time counter operation. In the BASIC TIME MODE (MODE REG. timer if the CLOCK RESET command ...
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CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE 4.1 Crystal Oscillation Circuit The PD4991A has an oscillation circuit consisting of one CMOS inverter stage, feedback resistor R oscillation stabilization resistor Figure 4-1 shows the equivalent circuit. The oscillation frequency ...
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CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE 4.2.1 Dependency on capacitance Figure 4-3 shows the dependency of oscillation frequency load capacitance C 2048 Hz output to TP1) where pF and C ...
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CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE 4.2.2 Dependency on temperature The oscillation frequency heavily fluctuates with temperature as shown in Figure 4-5. The temperature charac- teristics show a negative quadratic curve peaking at around 25 C. These characteristics are of ...
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CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE Figure 4-5. Oscillation Frequency f vs. Ambient Temperature T 2048.3 8.4 97.7 2048.2 4.2 48.8 2048 2048.0 –4.2 –48.4 2047.9 –8.4 –97.7 2047.8 –12.7 –146.5 2047.7 –16.9 –195.3 2047.6 2047 ...
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CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE 4.2.3 Dependency on supply voltage The oscillation characteristics also vary with supply voltage V the voltage for access, the higher the watch accuracy. The higher C and C , the better the dependency on ...
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CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE 4.3 Adjusting Oscillation Frequency The accuracy of the watch depends on the stability of the oscillation frequency. In the actual operating conditions, however mostly determined by the accuracy of adjustment of the ...
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CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE 4.4 Back-up Circuit Because the PD4991A is a CMOS IC, it can provide a back-up operation with a low-voltage battery. Figure 4- 8 shows an example of using a Ni-Cd battery for back-up, and ...
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CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE 4.5 Power-fail Circuit While the PD4991A is backed up, the CS The power-fail circuit fixes CS to low when the voltage of the +5-V power supply drops below the operating voltage 2 of the ...
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CHAPTER 4 ELECTRICAL SPECIFICATIONS AND INTERFACE Figure 4-12. Power-Fail Circuit (with PC2260V) PC2260V GND DLY RST + 0.33 F When the PC2260V is used, the power supply circuit and power-fail circuit of the system can ...
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Appendix 1. Specifications of PD4991A Absolute Maximum Ratings ( Parameter Supply voltage Input voltage range Output pin voltage Low-level output current (N-ch open drain) Operating temperature range Storage temperature range Electrical Specifications ( ...
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Write cycle timing 1 ADDRESS OUT D IN Write cycle timing 2 ( ADDRESS OUT APPENDIX ...
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Read cycle (Unless otherwise specified, V Parameter Symbol Cycle time t RC Address access time access time t ACS OE - output delay time output delay time t OLZ OE - output ...
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PLASTIC DIP (300 mil NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) ltem "K" to center ...
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PIN PLASTIC SOP (300 mil NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. APPENDIX 11 detail of ...
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Appendix 3. Differences between PD4991 and PD4991A The PD4991A improves the characteristics of the PD4991. The differences between the two are as follows: 1. Specifications Parameter Current consumption Current consumption Current consumption Input data setup time Input data hold time ...
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AC Timing Specification of PD4991 Timing Specification of PD4991A Function Parameter Valid range ADJUST BUSY flag on execution of ...
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Facsimile From: Name Company Tel. Address North America NEC Electronics Inc. Corporate Communications Dept. Fax: 1-800-729-9288 1-408-588-6130 Europe NEC Electronics (Europe) GmbH Technical Documentation Dept. Fax: +49-211-6503-274 South America NEC do Brasil S.A. Fax: +55-11-6465-6829 I would like to report ...