COM20020I-HD Standard Microsystems (SMSC), COM20020I-HD Datasheet - Page 61

• Manufacturer Part Number: COM20020I-HD
• Manufacturer: Standard Microsystems (SMSC)

Specifications of COM20020I-HD

• Number Of Transceivers: 1
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
SMSC COM20020I Rev D
D0-D7
**
Note 3:
A0-A2
Note 1:
Note 2: Any cycle occurring after a write to the Address Pointer Low Register
*
***:
nWR
nRD
nCS
T
T
T
T
t5
t1
t2
t3
t4
t6
t7
t8
t9
t10
Figure 8.9 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle
ARB
ARB
ARB
opr
be 30 nS measured from the later of nCS falling or Valid Data available.
nCS may become active after control becomes active, but the data setup time will now
is the period of operation clock. It depends on CKUP1 and CKUP0 bits
is the Arbitration Clock Period
is identical to T
is twice T
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5T
leading edge of the next nWR.
requires a minimum of 4T
of the next nWR.
Write cycle for Address Pointer Low Register occurring after a read from Data
Register requires a minimum of 5T
leading edge of nWR.
Address Setup to nWR Active
Address Hold from nWR Inactive
nCS Setup to WR Active
nCS Hold from nWR Inactive
Cycle Time (nWR
Valid Data Setup to nWR High
Data Hold from nWR High
nWR Low Width
nWR High Width
nRD
opr
to nWR Low
if SLOW ARB = 1
Parameter
Note 3
opr
t10
t1
if SLOW ARB = 0
t3
to Next
DATASHEET
ARB
from the trailing edge of nWR to the leading edge
ARB
ARB
)**
Page 61
VALID
from the trailing edge of nWR to the
from the trailing edge of nRD to the
t8
VALID DATA
4T
t6
30***
min
15
10
10
20
20
20
ARB
5
0
*
max
t7
t2
Note 2
t4
t9
t5**
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
t5
Revision 12-05-06