TXC-03303AIPQ Transwitch Corporation, TXC-03303AIPQ Datasheet - Page 40

• Manufacturer Part Number: TXC-03303AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03303AIPQ

• Lead Free Status / RoHS Status: Not Compliant

Address
1A
1B
17
18
19
6-0
7-0
6-0
7-0
7-0
Bit
7
7
DS2OOFn
CERROR
Symbol
C3CLKI
(n=7-1)
(n=7-0)
FMEn
TEST
TEST
TEST
Latched C-bit Status/DS2 Out Of Frame Bits: The bits in this register
location are the same bits listed in register location 03H, except the corre-
sponding bit latches on with an alarm. For example, CERROR latches to a
one on the first time C1 is 0. A microprocessor read cycle clears a set bit. If
a DS2 OOF remains true (a one), the corresponding bit relatches.
TranSwitch Test Register: Used for TranSwitch testing. No value is
required to be written into this register location.
C-Bit Parity C3 Clock Inhibit: A zero enables the M13E to generate an
extra clock pulse in the CCKT clock signal for clocking the C3 bit in from
external logic. A one disables the generation of the C3 clock pulse. This bit
must be set to 1 if the FEAC register 1CH is used to transmit FEAC codes
or if register 07H is used to send a remote loopback request via a double
word FEAC message (LBSEL = 1). If this bit is set to 0, then the FEAC mes-
sages are derived from the external C-bit interface.
TranSwitch Test Bits: Used for TranSwitch testing. No value is required to
be written into these bit locations.
TranSwitch Test Register: Used for TranSwitch testing. No value is
required to be written into this register location.
DS3 F-bits and M-bits in Error Counter: An 8-bit saturating counter that
counts the number of DS3 F-bits and DS3 M-bits that are in error since the
last read cycle. The counter is inhibited when DS3 loss of signal or out of
frame occurs. The counter is cleared when it is read by the microprocessor.
- 40 -
Description
Ed. 4, August 1998
TXC-03303
TXC-03303-MB
M13E