DJLXT380LE.B4 Cortina Systems Inc, DJLXT380LE.B4 Datasheet - Page 12

• Manufacturer Part Number: DJLXT380LE.B4
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT380LE.B4

• Lead Free Status / RoHS Status: Not Compliant

LXT380 — Octal E1 G.703 Transceiver
12
Table 1.
LXT380 Pin Description
LQFP
† DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S:
Pin #
10
12
11
7
7
8
8
9
Power Supply; N.C.: Not Connected.
PBGA
Pin #
D3
D3
D2
D2
D1
E1
E2
F4
TDATA6
Symbol I/O
TNEG6
TPOS6
TCLK6
MODE
MCLK
UBS6
GND
DI
DI
DI
DI
DI
DI
DI
DI
†
Transmit Negative Data Input.
Unipolar/Bipolar Select Input.
Transmit Positive Data Input.
Transmit Data Input.
Bipolar Mode:
TPOS/TNEG are active high NRZ inputs. TPOS indicates the transmission of
a positive pulse whereas TNEG indicates the transmission of a negative
pulse.
Unipolar Mode:
When TNEG/UBS is pulled High for more than 16 consecutive TCLK clock
cycles, unipolar I/O with HDB3 encode/decode is selected.
TDATA is the data input in unipolar I/O mode.
Transmit Clock Input.
Master Clock Input. This 2.048 Mhz reference clock is used to generate
several internal reference signals:
If MCLK is High, the PLL clock recovery circuit is disabled. In this mode the
LXT380 operates as simple data receiver.
Note: Wait state generation via RDY/ACK is not available in this mode.
If MCLK is Low, the complete receive path is powered down and the output
pins RCLK, RPOS and RNEG are switched to Tri-state mode.
MCLK is not required if the LXT380 is used as simple analog front-end
without clock recovery.
MCLK should be an independent free-running reference clock.
Mode Select Input. This pin is used to select the operating mode of the
LXT380. In Hardware Mode, the parallel processor interface is disabled and
hardwired pins are used to control configuration and report status. In Parallel
Host Mode, the parallel port interface pins are used to control configuration
and report status.
In Serial Host Mode, the serial interface pins: SDI, SDO, SCLK and CS are
used.
VCCIO 2 Serial Host Mode
For Serial Host Mode, this pin should connect to a resistive divider consisting
of two 10 k resistors across VCCIO and Ground.
Ground. This pin must be connected to Ground.
MODE
TPOS TNEG Selection
• Timing reference for the integrated high performance clock recovery unit
• Generation of RCLK signal during a loss of signal condition
• REFERENCE clock during a blue alarm transmit all ones condition
• Reference timing for the parallel processor wait state generation logic
H
0
1
0
1
L
0
0
1
1
Operating Mode
Hardware Mode
Parallel Mode
Space
Positive Mark
Negative Mark
Space
Description
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