BCM5208KPF Broadcom, BCM5208KPF Datasheet
BCM5208KPF
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BCM5208KPF Summary of contents
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Quad-Φ™ Transceiver The BCM5208 is a single-chip Quad 10/100BASE-TX/FX transceiver targeted at Fast Ethernet switches and segmentable repeaters. The device contains ...
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... Broadcom Corporation 16215 Alton Parkway P.O. Box 57013 Irvine, California 92619-7013 © 1999 by Broadcom Corporation All rights reserved Printed in the U.S.A. ...
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November 3, 1999 REVISION HISTORY REVISION # DATE SP1.8 July 13, 1998 SP2.0 March 5, 1999 5208-DS03-R November 3, 1999 Document 5208-DS03-R¥¥¥¥¥ CHANGE DESCRIPTION Preliminary Release Final Release: 1. Page 9, Table 4, VREF default condition changed. 2. Pages 10 ...
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BCM5208 Page November 3, 1999 Document 5208-DS03-R¥¥¥¥¥ ...
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November 3, 1999 Cover Page General Description Features Applications Revision History Section 1: Functional Description............................................................................................. 1 Overview ................................................................................................................................................ 1 Encoder / Decoder ................................................................................................................................. 1 Link Monitor............................................................................................................................................ 1 Carrier Sense ......................................................................................................................................... 2 Collision Detection ................................................................................................................................. 2 Carrier Integrity Monitor ......................................................................................................................... 2 ...
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... Auxiliary Status Summary Register......................................................................................................29 Interrupt Register .................................................................................................................................30 Auxiliary Mode 2 Register ....................................................................................................................31 10BASE-T Auxiliary Error & General Status Register..........................................................................32 Auxiliary Mode Register .......................................................................................................................33 Auxiliary Multiple PHY Register ...........................................................................................................34 Broadcom Test Register ......................................................................................................................35 Section 6: Timing and AC Characteristics ............................................................................. 36 Section 7: Electrical Characteristics....................................................................................... 47 Section 8: Application Examples ............................................................................................ 49 Section 9: Mechanical Information.......................................................................................... 51 Section 10: Ordering Information............................................................................................ 52 ...
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November 3, 1999 Figure 1: Functional Block Diagram ...........................................................................................Cover Page Figure 2: Pinout Diagram...........................................................................................................................12 Figure 3: Clock and Reset Timing .............................................................................................................36 Figure 4: Transmit Start of Packet Timing (100BASE-TX) ........................................................................37 Figure 5: Transmit End of Packet Timing (100 Base-TX) ..........................................................................38 ...
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... Table 23: 10BASE-T Auxiliary Error and General Status Register (Address 28d, 1Ch) ............................32 Table 24: Auxiliary Mode Register (Address 29d, 1Dh) .............................................................................33 Table 25: Auxiliary Multiple PHY Register (Address 30d, 1Eh)..................................................................34 Table 26: Broadcom Test (Address 31d, 1Fh) ...........................................................................................35 Table 27: Clock Timing...............................................................................................................................36 Table 28: Reset Timing ..............................................................................................................................36 Table 29: 100BASE-X Transmit Timing......................................................................................................37 Table 30: 10BASE-T Transmit Timing - Parallel Mode ...
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November 3, 1999 SECTION 1: FUNCTIONAL DESCRIPTION OVERVIEW The BCM5208 is a single-chip device containing four independent Fast Ethernet transceivers. Each performs all the physical layer interface functions for 100BASE-TX full-duplex or half-duplex Ethernet on CAT 5 twisted pair cable ...
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BCM5208 CARRIER SENSE In 100BASE-X modes, carrier sense is asserted asynchronously on the CRS pin as soon as activity is detected in the receive data stream. RXDV is asserted as soon as a valid start-of-stream delimiter (SSD) is detected. ...
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November 3, 1999 DIGITAL CLOCK RECOVERY/GENERATOR The all-digital clock recovery and generator block creates all internal transmit and receive clocks. The transmit clocks are locked to the 25 MHz clock input while the receive clocks are locked to the incoming ...
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BCM5208 V 0111 V 0111 V 0111 V 0111 V 0111 V 0111 V 0111 V 0111 V 0111 V 0111 * Treated as invalid code (mapped to 0111) when received in data field. ERROR TYPE Stream cipher error ...
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November 3, 1999 FAR-END FAULT Auto-Negotiation provides a Remote Fault capability for detection of asymmetric link failures. Since Auto-Negotiation is not available for 100BASE-FX, the BCM5208 implements the IEEE 802.3 standard Far-End Fault mechanism for the indication and detection of ...
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BCM5208 SERIAL LED MODES The BCM5208 supports several modes for providing LED and interrupt information as a serial bit stream. The LED data is presented on a single pin with a second pin providing a shift clock and a ...
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November 3, 1999 SECTION 2: HARDWARE SIGNAL DEFINITION TABLE Table 4 provides the pin descriptions for the BCM5208. PIN PIN LABEL TYPE MEDIA CONNECTIONS 60, 75, 82, RD+ {1: 61, 74, 83, RD− {1:4} 96 65, 70, ...
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BCM5208 PIN PIN LABEL TYPE 32, 207, I TXER {1:4} PD 156, 125 17, 190, O RXC {1:4} 3S 172, 140 19, 20, 21, RXD[3:0] {1} 23 192, 193, RXD[3:0] {2} 194, 195 O 3S 170, 169 RXD[3:0] {3} ...
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November 3, 1999 PIN PIN LABEL TYPE I 41 RPTR SER10 FDXEN/CIMEN PD I 104 F100 PU I 105 ANEN PU 58, 57, 56, I TXJAM {1: 116, 115 ER[1:0] PU ...
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BCM5208 PIN PIN LABEL TYPE 204, 185, SP100LED# O 177, 158 {1:4} XMTLED# {1:4} INTR# {1:4} 202, 183 179, 160 FDXLED# {1:4} Ser SDO# {2} RCVLED# {1:4} 201, 182, O ACTLED# {1:4} OD 180, 161 Ser SCLK# ...
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November 3, 1999 PIN PIN LABEL TYPE 62, 64, 67, 68, 71, 73, AGND 84, 86, 89, 90, 93 15, 30, 113, 127, 142, 153, DVDD 164, 175, 187, 198 5, 16, 31, 45, 112, 126, 141, DGND ...
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BCM5208 Figure 2 provides the pinout diagram for the BCM5208. TXD[2] {2} 1 OVDD 2 OGND 3 DVDD 4 DGND 5 CK25 6 PLLVDD 7 PLLGND 8 TXD[1] {2} 9 TXD[0] {2} 10 TXEN {2} 11 TXC {2}/CLK10 12 ...
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November 3, 1999 SECTION 4: OPERATIONAL DESCRIPTION RESETTING THE BCM5208 There are two ways to reset each transceiver in the BCM5208. A hardware reset pin has been provided which resets all internal nodes inside the chip to a known state. ...
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BCM5208 MULTI-SEGMENT REPEATERS The BCM5208 supports multi-segment repeaters by allowing each transceiver to connect to any of the MII interfaces. Interface selection is programmed through the Auxiliary Mode register (1Dh). When multiple transceivers are connected to the same MII ...
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November 3, 1999 MEDIA INDEPENDENT INTERFACE (MII) MANAGEMENT INTERFACE: REGISTER PROGRAMMING The BCM5208 fully complies with the IEEE 802.3u Media Independent Interface (MII) specification. The MII management interface registers of each port are serially written-to and read-from using a common ...
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BCM5208 MII CONTROL REGISTER The MII control register bit descriptions are shown in Table 7. Table 7: MII Control Register (Address 00d, 00h) BIT NAME 15 Reset 14 Loopback 13 Forced Speed Selection 12 Auto-Negotiation Enable 11 Power Down ...
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November 3, 1999 ISOLATE. Each individual PHY may be isolated from its Media Independent Interface by writing a “1” to bit 10 of the Control Register. All MII outputs will be tri-stated and all MII inputs will be ignored. Since ...
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... MII Address 00011 Broadcom Corporation has been issued an Organizationally Unique Identifier (OUI) by the IEEE bit number, 00- 10-18, expressed as hex values. That number, along with the Broadcom Model Number for the BCM5208 part, 13h, and Broadcom Revision number, 01h, is placed into two MII Registers. The translation from OUI, Model Number and Revision ...
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November 3, 1999 AUTO-NEGOTIATION ADVERTISEMENT REGISTER Table 10 shows the auto-negotiation advertisement register bit descriptions. Table 10: Auto-Negotiation Advertisement Register (Address 04d and 04h) BIT NAME 15 Next Page 14 Reserved 13 Remote Fault 12:11 Reserved Technologies 10 Advertise Pause ...
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BCM5208 . AUTO-NEGOTIATION LINK PARTNER (LP) ABILITY REGISTER Table 11 shows the auto-negotiation link partner ability register bit descriptions. Table 11: Auto-Negotiation Link Partner Ability Register (Address 05d, 05h) BIT NAME 15 LP Next Page 14 LP Acknowledge 13 ...
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November 3, 1999 . AUTO-NEGOTIATION EXPANSION REGISTER Table 12 shows the auto-negotiation expansion register bit descriptions. Table 12: Auto-Negotiation Expansion Register (Address 06d and 06h) BIT NAME 15:5 Reserved 4 Parallel Detection Fault 3 Link Partner Next Page Able 2 ...
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BCM5208 . 100BASE-X AUXILIARY CONTROL REGISTER The 100BASE-X auxiliary control register bit descriptions are shown in Table 14. Table 14: 100BASE-X Auxiliary Control Register (Address 16d, 10h) BIT NAME 15:14 Reserved 13 Transmit Disable 12 CIM Disable 11 Reserved ...
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November 3, 1999 RESERVED BITS. The Reserved bits of the 100BASE-X Auxiliary Control Register must be written as “0” at all times. Ignore the BCM5208 outputs when these bits are read. 100BASE-X AUXILIARY STATUS REGISTER See Table 15 for an ...
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BCM5208 BAD ESD DETECTED. The PHY will return a “1” in bit end of stream delimiter error has been detected since the last time this register was read. Otherwise it will return a “0”. RECEIVE ERROR ...
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November 3, 1999 AUXILIARY CONTROL/STATUS REGISTER Table 19 shows the auxiliary control/status register bit descriptions. Table 19: Auxiliary Control/Status Register (Address 24d, 18h) BIT NAME 15 Jabber Disable 14 Link Disable 13:8 Reserved 7:6 HSQ : LSQ 5:4 Edge Rate ...
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BCM5208 AUTO-NEGOTIATION INDICATOR. A read-only bit that indicates whether Auto-Negotiation has been enabled or disabled on the BCM5208. A combination of a “1” in bit 12 of the Control Register and a logic “1” on the ANEN input pin ...
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November 3, 1999 . AUXILIARY STATUS SUMMARY REGISTER The Auxiliary Status Summary Register contains copies of redundant status bits found elsewhere within the MII register space. Descriptions for each of these individual bits can be found associated with their primary ...
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BCM5208 INTERRUPT REGISTER Table 21 shows the bit descriptions for the interrupt register. Table 21: Interrupt Register (Address 26d, 1Ah) BIT NAME 15 FDX LED Enable 14 INTR Enable 13:12 Reserved 11 FDX Mask 10 SPD Mask 9 LINK ...
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November 3, 1999 AUXILIARY MODE 2 REGISTER The bit descriptions for auxiliary mode 2 register are shown in Table 22. Table 22: Auxiliary Mode 2 (Address 27d, 1Bh) BIT NAME 15:8 Reserved Block 10BASE-T Echo Mode 7 Traffic Meter LED ...
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BCM5208 10BASE-T AUXILIARY ERROR & GENERAL STATUS REGISTER The bit descriptions for the 10BASE-T auxiliary error and general status register are shown in Table 23. All Error bits in the Auxiliary Error Status Register are read-only and are latched ...
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November 3, 1999 SPEED INDICATION. A read-only bit that shows the true current operation speed of the BCM5208. A “1” bit indicates 100BASE-X operation, while a “0” indicates 10BASE-T. Note that while the Auto-Negotiation exchange is performed, the BCM5208 is ...
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BCM5208 AUXILIARY MULTIPLE PHY REGISTER The bit descriptions for the auxiliary multiple PHY register are shown in Table 25. Table 25: Auxiliary Multiple PHY Register (Address 30d, 1Eh) BIT NAME 15 HCD_TX_FDX 14 HCD_T4 13 HCD_TX 12 HCD_10BASE-T_FDX 11 ...
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... RXER Code mode is not available in 10BASE-T Serial mode. In 100BASE-X operation, the RXER code mode is always active. See Table 2. BROADCOM TEST REGISTER The Broadcom test register bits are reserved and should never be written. BIT NAME Document 5208-DS03-R¥¥¥¥¥ ...
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BCM5208 SECTION 6: TIMING AND AC CHARACTERISTICS All MII Interface pins comply with IEEE 802.3u timing specifications (See Reconciliation Sub-layer and Media Independent Interface in IEEE 802.3u timing specifications). All digital output timing specified at C Output rise/fall times ...
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November 3, 1999 Table 29 provides the parameters for 100BASE-X transmit timing. Figure 4 illustrates 100BASE-TX transmit start of packet timing and Figure 5 shows the 100BASE-TX transmit end of packet timing. PARAMETER TXC Cycle Time TXC High/Low Time TXC ...
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BCM5208 Figure 5: Transmit End of Packet Timing (100 Base-TX) CLOCK Note 1 TXEN TXD, DATA N TXER TD± CRS COL Note 1: CLOCK will be: TXC in DTE Mode CK25 in 100BASE-TX Repeater Mode Figure 30 provides the ...
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November 3, 1999 Figure 31 provides the parameters for 100BASE-X receive timing. Figure 6 illustrates 100BASE-TX receive start of packet timing and Figure 7 shows 100BASE-TX receive end of packet timing. Figure 8 shows 100BASE-TX receive packet premature end. Figure ...
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BCM5208 Figure 6: Receive Start of Packet Timing (100BASE-TX RD± RXC CRS RXEN (RPTR) RXDV RXD, RXER COL (Switch)* Figure 7: Receive End of Packet Timing (100BASE-TX) LAST DATA NIBBLE N4 N3 ...
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November 3, 1999 Figure 8: Receive Packet Premature End (100BASE-TX) DATA RD± I RXC CRS RXDV RXD RXER Figure 9: Link Failure or Stream Cipher Error During Receive Packet RXC CRS RXDV RXD RXER LINK/ LOCK Document 5208-DS03-R¥¥¥¥¥ ...
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BCM5208 Figure 10: False Carrier Sense Timing (100BASE-TX) RD± RXC CRS RXDV RXD 0 RXER Table 32 provides the parameters for 10BASE-T receive timing. 10BASE-T collision timing parameters are shown in Table 33. PARAMETER RXC Cycle ...
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November 3, 1999 Table 34, Table 35, Table 36 and Table 37 provide the parameters for loopback timing, auto-negotiation, and LED timing. Figure 11 illustrates serial mode LED timing. PARAMETER TXD to RXD Steady State Propagation Delay LPBK Setup Time ...
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BCM5208 RISE SCLK SDO_SETUP Bit 5/slice 4 SDO SFRM_SETUP SFRM Management data interface timing parameters are described in Table 38. Figure 12 and Figure 13 illustrate two types of management interface timing. PARAMETER MDC Cycle Time MDC High/Low MDC ...
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November 3, 1999 Figure 13: Management Interface Timing (with Preamble Suppression On) MDC MDIO D1 End of MDC/MDIO Cycle Note: Must wait two MDC clock cycles between MDIO commands when preamble suppression is activated (MII Register 1, Bit 6 set ...
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BCM5208 Table 40 and Figure 15 describe and show 10BASE-T serial repeater mode transmit timing. Table 40: 10BASE-T Serial Repeater Mode Transmit Timing PARAMETER CK10 Cycle Time CK10 Low Time CK10 High Time CK10 Rise Time CK10 Fall Time ...
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November 3, 1999 SECTION 7: ELECTRICAL CHARACTERISTICS This section covers the electrical characteristics of the BCM5208. Table 41 covers the absolute maximum ratings for the BCM5208. The recommended operating conditions are shown in Table 42. Table 43 gives the electrical ...
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BCM5208 SYM PARAMETER PINS Total Supply AVDD, DVDD, OVDD Current IVDD Individual PHY AVDD, DVDD, OVDD Supply Current IVDD All Digital Outputs High-Level V OH Output Voltage TD± {1:4} All Digital Outputs Low-Level V OL ...
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November 3, 1999 SECTION 8: APPLICATION EXAMPLES MAC MII{1} RJ45 Document 5208-DS03-R¥¥¥¥¥ Figure 16: Switch Application MAC MAC MII{2} MII{3} BCM5208 MAGNETICS RJ45 RJ45 ...
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BCM5208 Page 50 Figure 17: Repeater Application RD±{4} TD±{4} RD±{3} TD±{3} RD±{2} TD±{2} RD±{1} TD±{1} RD±{4} TD±{4} RD±{3} TD±{3} RD±{2} TD±{2} RD±{1} TD±{ ...
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November 3, 1999 SECTION 9: MECHANICAL INFORMATION D D1 θ θ 4 Millimeter Symbol Min A 0. 3.39 D 30.35 D1 27.90 E 30.35 E1 27.90 L 0.30 b 0.15 h 0.13 e 0.50 BSC c ...
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BCM5208 SECTION 10: ORDERING INFORMATION PART NUMBER PACKAGE BCM5208 KPF 208-PQFP Page 52 Table 44: Ordering Information AMBIENT TEMPERATURE 0° to 70° C (32° to 158° ...
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... BCM5208 Broadcom Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom Corporation is believed to be accurate and reliable. However, Broadcom Corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein ...
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