DJLXT905LE.C2 Cortina Systems Inc, DJLXT905LE.C2 Datasheet - Page 10

• Manufacturer Part Number: DJLXT905LE.C2
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT905LE.C2

• Number Of Receivers: 1
• Data Rate: 10Mbps
• Protocols Supported: 10BASE-T
• Operating Supply Voltage (typ): 5V
• Package Type: LQFP
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 5.25V
• Mounting: Surface Mount
• Pin Count: 32
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Not Compliant

LXT905 Transceiver
Datasheet
249271, Revision 5.1
5 November 2007
2.3
Table 2
2.4
Cortina Systems
schemes (Modes 1 through 4) provide this compatibility. The MD0 and MD1 mode select
pins determine controller compatibility modes (see
Specifications, on page 21
Transmit Function
The LXT905 Transceiver receives NRZ data from the controller at the TXD input, as
shown in
a Manchester encoder. The LXT905 Transceiver then transfers encoded data to the
twisted-pair network (TPO circuit). The advanced integrated pulse shaping and filtering
network produces the output signal on TPON and TPOP, shown in
Transceiver TPO Output Waveform, on page
filtered to meet the 10BASE-T jitter template. An internal, continuous resistor-capacitor
filter removes any high-frequency clocking noise from the pulse shaping circuitry.
Integrated filters simplify the design work required for FCC compliant EMI performance.
During idle periods, the LXT905 Transceiver transmits link integrity test pulses on the TPO
circuit (if LI is enabled and LBK is disabled).
Controller Compatibility Mode Options
Jabber Control Function
Figure 4
LXT905 Transceiver on-chip Watch-Dog Timer (WDT) prevents the DTE from locking into
a continuous transmit mode. When a transmission exceeds the time limit, the WDT
disables the transmit and loopback functions and activates the COL pin. Once the LXT905
Transceiver is in the jabber state, the TXD circuit must remain idle for a period of 0.25 to
0.75 seconds before it exits the jabber state.
®
Mode 1 - For Motorola* MC68EN360 or compatible controllers (AMD* AM7990)
Mode 2 - For Intel* 82596 or compatible controllers
Mode 3 - For Fujitsu* MB86950, MB86960 or compatible controllers (Seeq* 8005)
Mode 4 - For TI* TMS380C26 or compatible controllers
1. Seeq* controllers require inverters on CLKI, LBK, RCLK and COL.
LXT905 Universal 10BASE-T Transceiver with 3.3 V Support
is a state diagram of the LXT905 Transceiver jabber control function. The
Figure 1, LXT905 Transceiver Block Diagram, on page
for timing diagrams and parameters.
Controller Mode
9. The TPO output is pre-distorted and pre-
Table
2). Refer to
6, and passes it through
1
Figure 3, LXT905
Section 4.0, Test
2.3 Transmit Function
MD1
High
High
Low
Low
Page 10
MD0
High
High
Low
Low