LAN8187-JT Standard Microsystems (SMSC), LAN8187-JT Datasheet - Page 17

• Manufacturer Part Number: LAN8187-JT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN8187-JT

• Number Of Receivers: 1
• Data Rate: 10/100Mbps
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Mounting: Surface Mount
• Pin Count: 64
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Compliant

±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR
Datasheet
Chapter 4 Architecture Details
SMSC LAN8187/LAN8187i
4.1
4.2
4.2.1
4.2.2
M A C
C o n ve rte r
N R Z I
Functionally, the PHY can be divided into the following sections:
The data path of the 100Base-TX is shown in
100M Transmit Data Across the MII/RMII
For MII, the MAC controller drives the transmit data onto the TXD bus and asserts TX_EN to indicate
valid data. The data is latched by the PHY’s MII block on the rising edge of TX_CLK. The data is in
the form of 4-bit wide 25MHz data.
The MAC controller drives the transmit data onto the TXD bus and asserts TX_EN to indicate valid
data. The data is latched by the PHY’s MII block on the rising edge of REF_CLK. The data is in the
form of 2-bit wide 50MHz data.
4B/5B Encoding
The transmit data passes from the MII block to the 4B/5B encoder. This block encodes the data from
4-bit nibbles to 5-bit symbols (known as “code-groups”) according to
is mapped to 16 of the 32 possible code-groups. The remaining 16 code-groups are either used for
control information or are not valid.
The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles,
0 through F. The remaining code-groups are given letter designations with slashes on either side. For
example, an IDLE code-group is /I/, a transmit error code-group is /H/, etc.
Top Level Functional Architecture
100Base-TX Transmit
R J4 5
100Base-TX transmit and receive
10Base-T transmit and receive
MII or RMII interface to the controller
Auto-negotiation to automatically determine the best speed and duplex possible
Management Control to read status registers and write control registers
R M II 5 0 M h z b y 2 b its
M II 2 5 M h z b y 4 b its
E x t R e f_ C L K (fo r R M II o n ly)
N R Z I
o r
M L T -3
(fo r M II o n ly)
T X _ C L K
C o n ve rte r
M L T -3
Figure 4.1 100Base-TX Data Path
C A T -5
1 2 5 M b p s S e ria l
DATASHEET
M II
M L T -3
M L T -3
17
1 0 0 M
P L L
b y 4 b its
D rive r
®
2 5 M H z
Figure
Technology
T x
4.1. Each major block is explained below.
E n co d e r
4 B /5 B
M L T -3
M a g n e tic s
Table
2 5 M H z b y
5 b its
4.1. Each 4-bit data-nibble
Revision 1.6 (02-27-09)
S cra m b le r
a n d P IS O