PEF22827EL-V11 Lantiq, PEF22827EL-V11 Datasheet - Page 81

• Manufacturer Part Number: PEF22827EL-V11
• Manufacturer: Lantiq

Specifications of PEF22827EL-V11

• Lead Free Status / RoHS Status: Supplier Unconfirmed

7
This chapter describes the digital block operations. The operations of the analog block
are controlled in the digital block. Line driver block operations are described in
“Operation – Line Driver” on Page
Digital block operations are described below:
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7.1
Some pins are used as configuration pins, in addition to their normal tasks. During hard
reset (until the RSTO signal becomes inactive high) these pins are configured as input
pins. At the rising edge of RSTO, these pins are sampled and used for configuration
purposes. Immediately after reset, these pins assume their normal operation. During
reset, the user must ensure that these pins are defined appropriately to produce the
required configuration.
Table 27
pushed down with resistors.
Table 27
Normal Pin
Name
PCM_TSYNC
PCM_TSIG
PCM_TDATA
UTOD6
EOC_TEN
EOC_TCLK
Preliminary Data Sheet
“Configuration Pins During Hard Reset” on Page 81
“System Clock” on Page 82
“EEPROM” on Page 83
“Internal RAM Management” on Page 98
“The Boot Process” on Page 98
“Application Management” on Page 100
lists the configuration pins and their settings. All pins must be pulled up or
Operation – Digital Block
Configuration Pins During Hard Reset
Configuration Pins (page 1 of 2)
Pin #
J14
J12
J13
P14
D15
R8
Configuration
Pin Name
Reserved
Reserved
NT
EOC_TCLK
Reserved
Reserved
132.
81
Settings for Configuration
Must be 0 during reset.
Must be 1 during reset.
Must be 1 during reset.
0
1
0
1
0
1
B
B
B
B
B
B
SAR disabled. (Ethernet mode)
SAR enabled.
Work at LT side.
Work at NT side.
No synthesized impedance.
Standard VDSL mask used to
determine PSD levels.
Synthesized impedance. Firmware
may boost PSD to levels defined
by standard ADSL mask.
Operation – Digital Block
Rev. 1.1, 2005-01-30
VDSL6100i
PEF 22827