WBLXT9785HC.D0-865113 Cortina Systems Inc, WBLXT9785HC.D0-865113 Datasheet
WBLXT9785HC.D0-865113
Specifications of WBLXT9785HC.D0-865113
Related parts for WBLXT9785HC.D0-865113
WBLXT9785HC.D0-865113 Summary of contents
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... The Cortina Systems LXT9785 and LXT9785E are 8-port Fast Ethernet PHY Transceivers supporting IEEE 802.3 physical layer applications at 10 Mbps and 100 Mbps. These devices provide Serial/Source Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII) for switching and other independent port applications. The LXT9785 and LXT9785E are identical except for the IP telephony features included in the LXT9785E transceiver ...
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... SMII Interface.......................................................................................118 4.3.4.2 Source Synchronous-Serial Media Independent Interface ..................118 4.3.5 Configuration Management Interface ..................................................................118 4.3.6 MII Isolate ............................................................................................................118 4.3.7 MDIO Management Interface ..............................................................................119 4.3.8 MII Sectionalization..............................................................................................120 ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Contents Page 2 ...
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... Receive Error .......................................................................................................138 4.8.5 Out-of-Band Signaling .........................................................................................138 4.9 100 Mbps Operation .........................................................................................................141 4.9.1 100BASE-X Network Operations .........................................................................141 4.9.2 100BASE-X Protocol Sublayer Operations..........................................................141 4.9.2.1 PCS Sublayer ......................................................................................141 ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Contents Page 3 ...
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... Chassis Ground ...................................................................................162 5.2.3 MII Terminations ..................................................................................................162 5.2.4 Twisted-Pair Interface ..........................................................................................162 5.2.4.1 Magnetic Requirements .......................................................................163 5.2.5 The Fiber Interface ..............................................................................................163 5.2.6 LED Circuit...........................................................................................................164 5.3 Typical Application Circuits ...............................................................................................165 ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Contents Page 4 ...
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... Datasheet 249241, Revision 11.0 16 April 2007 6.0 Test Specifications ....................................................................................................................170 7.0 Register Definitions...................................................................................................................191 8.0 Package Specifications.............................................................................................................212 8.1 Top Label Markings ..........................................................................................................217 9.0 Ordering Information.................................................................................................................219 ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Contents Page 5 ...
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... SMII - 10BASE-T Receive Timing ...............................................................................................177 44 SMII - 10BASE-T Transmit Timing ..............................................................................................178 45 SS-SMII - 100BASE-TX Receive Timing .....................................................................................179 46 SS-SMII - 100BASE-TX Transmit Timing ....................................................................................180 47 SS-SMII - 100BASE-FX Receive Timing .....................................................................................180 48 SS-SMII - 100BASE-FX Transmit Timing ....................................................................................181 ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figures Page 6 ...
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... Example of Top Marking Information Labeled as Cortina Systems, Inc. .....................................217 70 Example of Top Marking Information Labeled as Intel Corporation* ...........................................217 71 Example of Top Marking Information Labeled as Level One Communications* .........................218 72 Ordering Information - Sample ....................................................................................................220 ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figures Page 7 ...
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... Global Hardware Configuration Settings ....................................................................................126 43 SMII Signal Summary ..................................................................................................................129 44 RX Status Encoding Bit Definitions .............................................................................................134 45 SS-SMII .......................................................................................................................................134 46 4B/5B Coding .............................................................................................................................142 47 DTE Terms ..................................................................................................................................148 48 Next Page Message #5 Code Word Definitions ..........................................................................151 ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Tables Page 8 ...
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... Quick Status Register (Address 17, Hex 11) ...............................................................................200 95 Interrupt Enable Register (Address 18, Hex 12)..........................................................................201 96 Interrupt Status Register (Address 19, Hex 13)...........................................................................203 97 LED Configuration Register (Address 20, Hex 14) ......................................................................204 98 Receive Error Count Register (Address 21, Hex 15)...................................................................205 ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Tables Page 9 ...
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... Cable Diagnostics Register (Address 29, Hex 1D)......................................................................209 102 Register Bit Map ..........................................................................................................................210 103 241-Ball BGA23 Package Dimensions ........................................................................................214 104 196-Ball BGA15 Package Dimensions (LXT9785MBC ) .............................................................216 105 Product Information .....................................................................................................................219 ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Tables Page 10 ...
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... All Globally added LEDn_3 to BGA15. 229 Added Figure 68 “Cortina Systems ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Revision 11.0 Revision Date: 16 April 2007 Revision Number: 010 Revision Date: 30-Mar-2006 Table 15, Power Supply Signal Descriptions – Table 34, Power Supply Signal Descriptions – ...
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... Modified/added text under Section 4.3.2, “Internal Loopback”. 121 Modified text under Section 4.3.6, “MII Isolate”. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Revision Number: 007 Revision Date: August 28, 2003 ® ® LXT9785 and Cortina Systems LXT9785E RMII 208-Pin PQFP ® ...
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... Modified text under Section 4.10.4, “Jabber”. 152 Modified first paragraph under Section 4.11, “DTE Discovery Process”. 153 Modified Item 1 of Section 4.11.2, “Interaction between Processor, MAC, and PHY”. 154 Modified second paragraph under Section 4.11.4, “DTE Discovery Process Flow”. 155 Added Section 4.11.5, “ ...
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... Added Figure 102 “Cortina Systems 227 Modified table and figure under Section 9.0, “Ordering Information”. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Revision Number: 007 Revision Date: August 28, 2003 ® LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing ® ...
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... Modified first sentence under Section 4.10.4, “Jabber”. 152 Modified first paragraph of Section 4.11, “DTE Discovery Process”. 153 Modified Item 1 of Section 4.11.2, “Interaction between Processor, MAC, and PHY”. 158 Modified Section 4.12.3, “Out-of-Band Signaling”. Added sentence to end of first paragraph. 166 Replaced text under Section 5.2.5, “ ...
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... Modified Figure 57 “RMII - 10BASE-T Receive Timing” and Table 53 “RMII - 10BASE-T Receive Timing 133 Parameters” ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Revision Date: June 10, 2003 Revision Number: 005 Revision Date: January 2002 ® LXT9785/LXT9785E Miscellaneous Signal Descriptions” (Added ® ...
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... Trim Enable Register: Modified table (DTE Discovery). 141 Modified Register Bit Map table. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Revision Number: 005 Revision Date: January 2002 Revision Number: 003 Revision Date: April 2001 Revision History ...
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... LXT9785/LXT9785E Specification Update ® Cortina Systems LXT9785/LXT9785E 100BASE-FX Fiber Optic Transceivers: Connecting a PECL/LVPECL Interface IP Telephony and DTE Discovery Using Cortina Systems ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1.0 Introduction ® LXT9785 and LXT9785E Document Number 249509 249357 250781 ® ...
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... MDINT_L 2 TxDatan Mgmt Counters Register Set Port LED Drivers 3 LEDn_[3:1]_L RxDatan ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 8-Port Global Functions Management / Mode Select Logic & LED Drivers Register Set Manchester 10 TP Encoder Pulse Driver Parallel/Serial ...
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... Weak Internal Pull-Down 3.1.1 PQFP Pin Assignments – RMII Configuration Figure 2 and Table 2, RMII PQFP Pin List, on page 22 PQFP pin assignments. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.0 Pin/Ball Assignments and Signal Descriptions provide LXT9785/LXT9785E RMII Page 20 ...
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... TxData2_1 ..... 43 REFCLK0 ..... 44 RxData1_1 ..... 45 RxData1_0 ..... 46 VCCIO ..... 47 GNDIO ..... 48 CRS_DV1 ..... 49 RxER1/PAUSE ..... 50 TxEN1 ..... 51 TxData1_0 ..... 52 ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Part # LXT9785/9785E XX FPO # XXXXXXXX BSMC 3.1 PQFP Pin Assignments 156 ....... TPFIN7 155 ....... GNDR7 154 ....... TPFOP7 153 ....... TPFON7 152 ....... VCCT6/7 151 ...
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... MDIO1 SL, IP OD, TS, 26 MDINT1_L SL TS, 27 RxData3_1 ID 28 RxData3_0 VCCIO – ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for Full Pin Symbol Description 30 GNDIO Table 5 31 CRS_DV3 Table 5 Table 13 32 RxER3 Table 5 33 TxEN3 Table 5 34 ...
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... SL, IP OD, TS, 82 LED0_1_L SL AMDIX_EN I, ST MDDIS I, ST CFG_3 I, ST CFG_2 I, ST, ID ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for Full Pin Symbol Description 87 CFG_1 Table 5 88 ADD_4 89 ADD_3 Table 5 90 ADD_2 Table 5 91 ADD_1 Table 5 ...
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... VCCR7 – 159 NC – 160 NC – 161 SD4 I 162 SD5 I ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for Full Pin Symbol Description Table 11 163 GNDPECL Table 15 164 VCCPECL Table 15 165 SD6 Table 11 166 SD7 ...
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... O, TS, 205 RxData6_1 ID 206 RxData6_0 O, TS 207 GNDIO – 208 VCCIO – ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for Full Description Table 5 Table 15 Table 15 Table 5 Table 5 Table 15 Table 5 Table 5 Table 5 Table 5 Table 5 Table 5 Table 5 ...
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... REFCLK0 ..... 44 NC ..... 45 RxData1 ..... 46 VCCIO ..... 47 GNDIO ..... 48 NC ..... 49 PAUSE ..... 50 NC ..... 51 TxData1 ..... 52 ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.1 PQFP Pin Assignments provide the LXT9785/LXT9785E LXT9785/9785E XX Rev # XXXXXXXX BSMC 156 .......TPFIN7 155 .......GNDR7 154 .......TPFOP7 153 .......TPFON7 152 .......VCCT6/7 151 ...
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... MDIO1 SL MDINT1_L TS, SL RxData3 VCCIO 30 GNDIO TxData3 ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for Full 1 Pin Symbol Description – Table 16 35 SYNC0 Table Table 13 37 RxData2 – Table 16 38 GNDIO I, ID Table – Table 16 ...
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... I, ST CFG_2 I, ST CFG_1 I, ST ADD_4 I, ST ADD_3 I, ST ADD_2 I, ST ADD_1 I, ST, ID ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for Full 1 Pin Symbol Description OD, 92 ADD_0 TS, Table 14 93 TxSLEW_1 94 TxSLEW_0 OD, Table 14 95 SD_2P5V IP 96 ...
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... SD5 163 GNDPECL 164 VCCPECL 165 SD6 166 SD7 167 TDI I, ST, IP ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for Full 1 Pin Symbol Description – Table 15 168 TDO – Table 15 169 TMS Table 11 170 ...
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... NC 203 TxData7 204 SYNC1 205 NC 206 RxData6 O, TS 207 GNDIO 208 VCCIO ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for Full 1 Description OD, Table 14 IP OD, Table 5 IP – Table 15 – Table 15 Table 16 ID Table 6 – ...
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... REFCLK0 ..... 44 RxData1 ..... 45 NC ..... 46 VCCIO ..... 47 GNDIO ..... 48 NC ..... 49 PAUSE ..... 50 NC ..... 51 TxData1 ..... 52 ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Part # LXT9785/9785E XX XXXXXXXX FPO # BSMC 3.1 PQFP Pin Assignments provide the LXT9785/ 156....... TPFIN7 155....... GNDR7 154....... TPFOP7 153....... TPFON7 152 ...
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... SL, IP OD, TS, 26 MDINT1_L SL TS, 27 RxData3 VCCIO 30 GNDIO TxCLK0 ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for Full 1 Pin Symbol Description – Table 16 34 TxData3 – Table 16 35 TxSYNC0 Table 13 36 RxData2 – Table 16 Table Table 16 ...
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... TxSLEW_1 I, ST TxSLEW_0 I, ST SD_2P5V I, ST SD0 97 SD1 98 VCCPECL ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for Full 1 Pin Symbol Description 99 GNDPECL Table 14 100 SD2 Table 14 101 SD3 102 NC Table 14 103 VCCR0 104 TPFIP0 Table 14 ...
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... I, ST, IP 170 TCK I, ST, ID 171 TRST_L I, ST, IP 172 NC 173 G_FX/TP_L I, ST, ID 174 PWRDWN I, ST, ID ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for Full 1 Pin Symbol Description Table 11 175 RESET_L – Table 15 176 SECTION Table 11 177 ModeSel0 ...
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... Revision 11.0 16 April 2007 Pin Symbol Type O, TS, 205 RxData6 206 NC 207 GNDIO 208 VCCIO ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for Full 1 Description Table 8 ID – Table 16 – Table 15 – Table 15 3.1 PQFP Pin Assignments ...
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... RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W Power-Down modes and during H/W reset. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description Reference Clock ...
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... RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W Power-Down modes and during H/W reset. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description Transmit Data - Port 3 ...
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... RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W Power-Down modes and during H/W reset. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description Receive Data - Port 6 ...
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... The IP/ID resistors are disabled during H/W Power-Down mode. 3. RxData[0:7] outputs are three-stated in Isolation and hardware power-down modes and during hardware reset. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Type Signal Description Transmit Data - Ports 0-7. ...
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... RxData[0:7], RxSYNC[0:1], and RxCLK[0:1] outputs are three-stated in Isolation and H/W Power-Down modes and during H/W reset. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description SS-SMII Transmit Synchronization. ...
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... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description Management Data Input/Output. Bidirectional serial data channel for communication between the PHY and MAC or switch ASIC. Only MDIO0 I/O, TS, SL, MDIO0 is used when 1x8 port sectionalization is MDIO1 IP selected. In 2x4 port sectionalization mode, MDIO0 accesses ports 0-3 and MDIO1 accesses ports 4-7 ...
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... MDI mode]. 3. Switched to Outputs (see TPFOP/N description) when not in fiber mode and MDIX is not active [that is, twisted-pair, non-crossover MDI mode]. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description2,3 Signal Detect 2.5 Volt Interface. ...
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... Three-State-able Output Slew-rate Limited Output Weak Internal Pull-Up Weak Internal Pull-Down. 2. The IP/ID resistors are disabled during hardware power-down mode. 3. The LINKHOLD ability is available only for stepping 4 (Revision D0). ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description Test Data Input. ...
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... Reset Register bit 0.15. When held Low, all outputs are forced to inactive state. Pin is not on JTAG chain. Address <4:0>. Sets base address. Each port adds its port number (starting with 0) to this address to determine its PHY address. ADD_4 Port 0 Address = Base ADD_3 ...
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... Three-State-able Output Slew-rate Limited Output Weak Internal Pull-Up Weak Internal Pull-Down. 2. The IP/ID resistors are disabled during hardware power-down mode. 3. The LINKHOLD ability is available only for stepping 4 (Revision D0). ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description Auto MDIX Enable Default. ...
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... Three-State-able Output Slew-rate Limited Output Weak Internal Pull-Up Weak Internal Pull-Down. 2. The IP/ID resistors are disabled during hardware power-down mode. 3. The LINKHOLD ability is available only for stepping 4 (Revision D0). ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description FIFO Select <1:0>. ...
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... The IP/ID resistors are disabled during H/W Power-Down mode pin is an output or an I/O, the IP/ID resistors are also disabled when the output is enabled. 3. The LED outputs are three-stated in H/W Power-Down mode and during H/W reset. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description Port 0 LED Drivers 1-3 ...
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... Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description Port 5 LED Drivers 1-3. ...
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... Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Symbol Type Signal Description Analog Power Supply - Transmit. ...
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... Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down. Table 17 Receive FIFO Depth Considerations FIFOSEL1 ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description NC – No Connection. Register 18.15 FIFOSEL0 Value 0 ...
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... LXT9785/LXT9785E 241-ball BGA23 ball locations for RMII, SMII, and SS-SMII. Figure 5 241-Ball BGA23 Assignments (Top View Ball ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers A10 A11 A12 B10 B11 B12 C10 C11 C12 D10 D11 D12 E10 E11 E12 F3 ...
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... GNDD B7 – GNDD C5 – GNDD C13 – GNDD C17 – GNDD D1 – ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference 1 for Full Signal Description Table 32 GNDD Table 32 GNDD Table 32 GNDD Table 32 GNDD Table 32 GNDD Table 32 ...
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... G4 SO, IP OD, TS, LED4_1_L K16 SL, IP OD, TS, LED4_2_L K17 SL, IP OD, TS, LED4_3_L J17 SL, IP ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference 1 for Full Signal Description Table 34 LED5_1_L Table 34 LED5_2_L Table 34 Table 34 LED5_3_L Table 34 Table 34 LED6_1_L Table 34 ...
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... No Ball L8 – No Ball L9 – No Ball L10 – No Ball L11 – No Ball L11 – ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference 1 for Full Signal Description – No Ball – No Ball – No Ball No Ball – No Ball – No Ball – ...
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... AO/AI TPFIP2 R6 AO/AI TPFIP3 T8 AO/AI TPFIP4 T9 AO/AI TPFIP5 U13 AO/AI TPFIP6 R12 AO/AI ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference 1 for Full Signal Description Table 24 TPFIP7 Table 32 TPFON0 Table 24 TPFON1 Table 32 TPFON2 Table 24 TPFON3 Table 32 ...
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... VCCT N6 – VCCT N7 – VCCT N9 – VCCT N11 – VCCT N12 – ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference 1 for Full Description Table 24 Table 24 Table 24 Table 24 Table 24 Table 32 Table 32 Table 34 Table 34 Table 34 Table 34 Table 34 ...
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... I, ST, ID B11 TxEN4 TS, B12 CRS_DV4 SL, ID B13 TxData5_0 I, ID B14 RxData5_0 O, TS ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Ball Signal Full Description Table 34 B15 RxData5_1 Table 34 B16 CRS_DV6 Table 24 B17 RxData6_1 Table 24 C1 ...
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... F7 No ball – ball – Ball – F10 No Ball – F11 No Ball – ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Ball Signal Full Description F12 No Ball Table 24 F13 GNDD Table 24 F14 RxData7_1 Table 34 F15 NC ...
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... I, ST, IP OD, TS, K2 LED0_2_L SL, IP OD, TS, K3 LED0_1_L SL – Ball – Ball – ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Ball Signal Full Description Table Ball – K8 GNDD – K9 GNDD – K10 GNDD Table 35 K11 ...
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... P10 VCCR – P11 VCCR – P12 VCCR – P13 GNDR – ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Ball Signal Full Description – P14 GNDT – P15 SD4 – P16 SD5 Table 34 ...
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... CFG_1 M1 I, ST, ID CFG_2 L3 I, ST, ID CFG_3 TS, FIFOSEL0 A12 SL, ID ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Full Description Table 30 Table 34 Table 30 Table 34 Table 30 Table 34 Table 30 Table 34 Table 30 Table 34 Table 30 Table 34 Table 30 ...
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... GNDT R3 – GNDT R5 – GNDT R15 – GNDT R17 – GNDT T17 – ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Signal Full Description Table 34 GNDT Table 34 GNDT Table 34 GNDT Table 34 GNDT Table 34 GNDT Table 34 ...
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... B12 – NC B15 – NC B16 – NC B17 – – – – ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Signal Full Description NC Table 33 NC Table Table Table 33 NC Table 33 NC Table 28 NC Table 28 NC Table 28 ...
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... M9 – Ball – Ball – Ball – Ball N8 – ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Signal Full Description – No Ball – PAUSE – – PREASEL – PWRDWN – REFCLK0 – REFCLK1 – RESET_L – ...
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... TxData3 TxData4 A11 I, ID TxData5 B13 I, ID TxData6 D13 I, ID TxData7 E14 I, ID ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Signal Full Description Table 30 TxSLEW_0 Table 30 TxSLEW_1 Table 30 VCCD Table 30 VCCD Table 30 VCCD Table 30 ...
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... B13 TxData5 I, ID B14 RxData5 O, TS, ID B15 NC – B16 NC – B17 NC – ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Ball Signal Full Description Table 34 C1 VCCIO Table 34 C2 RxData0 Table 26 C3 TxData1 Table 35 C4 ...
Page 67
... NC – OD, TS, F16 LED7_3_L SL, IP OD, TS, F17 LED7_2_L SL, IP OD, TS, G1 LED2_3_L SL – ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Ball Signal Full Description Table 35 G3 LED3_2_L Table 35 G4 LED3_3_L Table 34 Table Table Ball – ...
Page 68
... K13 No Ball – K14 SGND – K15 NC – OD, TS, K16 LED4_1_L SL, IP ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Ball Signal Full Description Table 33 K17 LED4_2_L Table 35 L1 MDDIS L2 CFG_3 Table 33 L3 CFG_2 ...
Page 69
... R2 TPFIP0 AO/AI R3 GNDT – R4 TPFON1 AO/AI R5 GNDT – R6 TPFIP2 AO/AI ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Ball Signal Full Description Table 32 R7 GNDR Table 29 R8 TPFIN3 Table 29 R9 GNDR Table 34 R10 TPFON4 ...
Page 70
... GNDD B7 – GNDD C5 – GNDD C13 – GNDD C17 – GNDD D1 – ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Full Description Table 30 Table 34 Table 30 Table 34 Table 30 Table 34 Table 34 Reference for 1 Signal Full Description Table 32 ...
Page 71
... LED1_2_L J3 SL, IP OD, TS, LED1_3_L H1 SL, IP OD, TS, LED2_1_L H2 SL, IP OD, TS, LED2_2_L H3 SL, IP ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Signal Full Description Table 34 LED2_3_L Table 34 LED3_1_L Table 34 LED3_2_L Table 34 Table 34 LED3_3_L Table 34 Table 34 LED4_1_L Table 34 ...
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... NC H14 – – NC J13 – – NC K15 – ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Signal Full Description Table 35 NC/ LINKHOLD Table 35 No ball Table 35 No ball Table 35 No ball Table 35 No Ball Table 35 ...
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... I, ST, ID SD0 P2 I SD1 N4 I SD2 P3 I SD3 N5 I SD4 P15 I ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Signal Full Description – SD5 – SD6 – SD7 – SECTION – SGND – TCK – ...
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... VCCR P7 – VCCR P8 – VCCR P9 – VCCR P10 – VCCR P11 – ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Signal Full Description Table 30 VCCR Table 30 VCCT Table 30 VCCT Table 30 VCCT VCCT Table 31 VCCT Table 27 ...
Page 75
... B14 NC – B15 RxData5 O, TS, ID B16 NC – B17 RxData6 O, TS VCCIO – – ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Ball Signal Full Description Table 34 C3 TxData1 Table Table 35 C5 GNDD Table Table 35 C7 ...
Page 76
... OD, TS, F17 LED7_2_L SL, IP OD, TS, G1 LED2_3_L SL – OD, TS, G3 LED3_2_L SL, IP OD, TS, G4 LED3_3_L SL, IP ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Ball Signal Full Description Table Table Ball – Ball Table Ball – Ball Table 34 ...
Page 77
... SGND – K15 NC – OD, TS, K16 LED4_1_L SL, IP OD, TS, K17 LED4_2_L SL MDDIS I, ST, ID ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Ball Signal Full Description L2 CFG_3 Table 33 L3 CFG_2 Table 33 L4 ADD_4 L5 VCCPECL Table Ball – ...
Page 78
... AO/AI R5 GNDT – R6 TPFIP2 AO/AI R7 GNDR – R8 TPFIN3 AO/AI R9 GNDR – ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Ball Signal Full Description Table 34 R10 TPFON4 Table 34 R11 GNDR – R12 TPFIP6 Table 34 R13 GNDR – ...
Page 79
... Designation, an underscore, and the serial designation. For example, a set of three Port Configuration signals would be identified as RxData0_0 and RxData0_1, RxData1_0 and RxData1_1, and RxData2_0 and RxData2_1. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for 1 Full Description Table 34 ...
Page 80
... RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W Power-Down modes and during H/W reset. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description Reference Clock ...
Page 81
... RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W Power-Down modes and during H/W reset. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description Receive Data - Port 0 ...
Page 82
... RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W Power-Down modes and during H/W reset. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description Receive Data - Port 7 ...
Page 83
... The IP/ID resistors are disabled during H/W Power-Down mode. 3. RxData[0:7] outputs are three-stated in Isolation and hardware power-down modes and during hardware reset. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Type Signal Description Transmit Data - Ports 0-7. ...
Page 84
... RxData[0:7], RxSYNC[0:1], and RxCLK[0:1] outputs are three-stated in Isolation and H/W Power-Down modes and during H/W reset. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description SS-SMII Transmit Synchronization. ...
Page 85
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description Management Data Input/Output. Bidirectional serial data channel for communication between the PHY and MAC or switch ASIC. Only MDIO0 I/O, TS, SL, MDIO0 is used when 1x8 port sectionalization is MDIO1 IP selected. In 2x4 port sectionalization mode, MDIO0 accesses ports 0-3 and MDIO1 accesses ports 4-7 ...
Page 86
... MDI mode]. 3. Switched to Outputs (see TPFOP/N description) when not in fiber mode and MDIX is not active [that is, twisted-pair, non-crossover MDI mode]. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description2,3 Signal Detect 2.5 Volt Interface. ...
Page 87
... The IP/ID resistors are disabled during H/W Power-Down mode pin is an output or an I/O, the IP/ID resistors are also disabled when the output is enabled. 3. TDO output is three-stated in H/W Power-Down mode and during H/W reset. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description Test Data Input ...
Page 88
... Three-State-able Output Slew-rate Limited Output Weak Internal Pull-Up Weak Internal Pull-Down. 2. The IP/ID resistors are disabled during hardware power-down mode. 3. The LINKHOLD ability is available only for stepping 4 (Revision D0). ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description Tx Output Slew Controls 0 and 1 Defaults. ...
Page 89
... LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description Address <4:0>. Sets base address. Each port adds its port number (starting with 0) to this address to determine its PHY address. ADD_4 Port 0 Address = Base ADD_3 Port 1 Address = Base + 1 ADD_2 ...
Page 90
... Three-State-able Output Slew-rate Limited Output Weak Internal Pull-Up Weak Internal Pull-Down. 2. The IP/ID resistors are disabled during hardware power-down mode. 3. The LINKHOLD ability is available only for stepping 4 (Revision D0). ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description MDIX Select Default. ...
Page 91
... Three-State-able Output Slew-rate Limited Output Weak Internal Pull-Up Weak Internal Pull-Down. 2. The IP/ID resistors are disabled during hardware power-down mode. 3. The LINKHOLD ability is available only for stepping 4 (Revision D0). ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description FIFO Select <1:0>. ...
Page 92
... The IP/ID resistors are disabled during H/W Power-Down mode pin is an output or an I/O, the IP/ID resistors are also disabled when the output is enabled. 3. The LED outputs are three-stated in H/W Power-Down mode and during H/W reset. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description Port 0 LED Drivers 1-3 ...
Page 93
... Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description Port 5 LED Drivers 1-3. ...
Page 94
... Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Symbol Type Signal Description Analog Power Supply - Receive. ...
Page 95
... K15 1. Type Column Coding Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output weak Internal Pull-up weak Internal pull- Down. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Symbol Type Signal Description NC – ...
Page 96
... LXT9785/LXT9785E Datasheet 249241, Revision 11.0 16 April 2007 Table 36 Receive FIFO Depth Configurations FIFOSEL1 ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.4 BGA23 Signal Descriptions FIFOSEL0 Register 18.15 Value Register 18.14 Value Page 96 ...
Page 97
... Table 37, LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name, on page 98 • Table 38, LXT9785MBC BGA15 Ball List in Alphanumeric Order by Ball Location (SMII/SS-SMII), on page 102 Figure 6 196-Ball BGA15 Assignments (Top View ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers A10 A11 B10 B11 ...
Page 98
... H11 AVSS J9 AVSS J10 AVSS J11 AVSS K11 AVSS L11 I, ST, CFG_1 M10 ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for Full Signal Description Name Table 39 CFG_2 ID Table 39 CFG_3 ID FIFOSEL0 Table 39 IP FIFOSEL1 – Table 39 GNDD – ...
Page 99
... SL, IP OD, LED3_1_L P6 TS, SL, IP OD, LED3_2_L N6 TS, SL, IP OD, LED3_3_L M6 TS, SL, IP ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for Full Signal Description Name – Table 39 LED4_1_L – Table 39 – Table 39 LED4_2_L – Table 39 – Table 39 – ...
Page 100
... J2 S RxData3_S RxData3_S O, TS RxData4_S RxData4_S O, TS RxData5_S ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for Full Signal Description Name – Table 39 RxData5_S S – Table 39 RxData6_S – Table 39 RxData6_S – Table 39 S – Table 39 RxData7_S – ...
Page 101
... TXSLEW_1 M12 VCCD D7 VCCD L7 VCCIO D4 VCCIO F4 VCCIO H4 VCCIO L3 VCCIO L5 ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for Full Description Table 39 Table 39 Table 39 Table 39 Table 39 Table 39 Table 39 Table 39 Table 39 Table 39 Table 39 Table 39 IP Table 39 Table 39 Table 39 ...
Page 102
... RxData6_S GNDD B6 LED7_1_L SL LED6_2_L SL LED5_1_L SL LED4_1_L SL, IP B10 GNDD ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for Full Ball Description – Table 39 B11 – Table 39 B12 – Table 39 B13 O, Table 39 B14 I, ID Table 39 C1 FIFOSEL1 ...
Page 103
... AVSS F11 AVSS F12 AVCC F13 TPON4 AO/AI F14 TPOP4 G1 RXCLK TS ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for Full Ball Description – Table 39 G3 – Table 39 G4 – Table 39 G5 Table 39 G6 Table 39 G7 ...
Page 104
... L13 TPIP2 AI/AO L14 TPIN2 AI/AO M1 RxData1_SS TS RxData1_S RxData0_SS TS, ID ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for Full Ball Description – Table 39 M4 Table 39 M5 Table 39 M6 LED3_3_L I, ID Table 39 Table 39 M7 LED2_3_L I, ID Table 39 – ...
Page 105
... P10 ADD_3 P11 GNDD P12 TPIP0 AI/AO P13 TPOP0 AO/AI P14 TPON1 AO/AI ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference for Full Description – Table 39 – Table 39 – Table 39 Table 39 ID OD, TS, Table 39 OD, TS, ...
Page 106
... Switched to TPIP/N Inputs when MDIX is not active (twisted-pair, non-crossover MDI mode). 3. Switched to TPOP/N Outputs when MDIX is not active (twisted-pair, non-crossover MDI mode). ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Type Signal Description SMII/SS-SMII Common Signal Descriptions ...
Page 107
... A4, C6 MDIO Control Interface Signal Descriptions Management Data Input/Output. I/O, TS, Bidirectional serial data channel for communication N5 SL, IP between the PHY and MAC or switch ASIC. Refer to Figure 21 on page 136. Management Data Interrupt. OD, TS, When Register bit 18 active Low output on this P5 SL, Pin indicates status change ...
Page 108
... Switched to TPIP/N Inputs when MDIX is not active (twisted-pair, non-crossover MDI mode). 3. Switched to TPOP/N Outputs when MDIX is not active (twisted-pair, non-crossover MDI mode). ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Type Signal Description Management Data Clock. Clock for the MDIO serial data channel. Maximum frequency is 20 MHz ...
Page 109
... Switched to TPIP/N Inputs when MDIX is not active (twisted-pair, non-crossover MDI mode). 3. Switched to TPOP/N Outputs when MDIX is not active (twisted-pair, non-crossover MDI mode). ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Type Signal Description Tx Output Slew Controls 0 and 1 Defaults. ...
Page 110
... Switched to TPIP/N Inputs when MDIX is not active (twisted-pair, non-crossover MDI mode). 3. Switched to TPOP/N Outputs when MDIX is not active (twisted-pair, non-crossover MDI mode). ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Type Signal Description Auto MDI/MDIX Enable Default. ...
Page 111
... Switched to TPIP/N Inputs when MDIX is not active (twisted-pair, non-crossover MDI mode). 3. Switched to TPOP/N Outputs when MDIX is not active (twisted-pair, non-crossover MDI mode). ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Type Signal Description Port 1 LED Drivers 1-3. ...
Page 112
... Down. 2. Switched to TPIP/N Inputs when MDIX is not active (twisted-pair, non-crossover MDI mode). 3. Switched to TPOP/N Outputs when MDIX is not active (twisted-pair, non-crossover MDI mode). ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Type Signal Description Analog Ground. – ...
Page 113
... Sectionalization • Hardware control pins: — PAUSE — MDIX — MDDIS — PWRDWN — Lower three PHY address (out of five PHY address bits) • Extended temperature Note: Unless otherwise noted, all information in this document applies to the LXT9785 and LXT9785E. 4.1.1 OSP™ ...
Page 114
... If the PHY device on the other side of the link supports auto-negotiation, the LXT9785/LXT9785E auto- negotiates with it using Fast Link Pulse (FLP) Bursts. If the PHY partner does not support auto-negotiation, the LXT9785/LXT9785E automatically detects the presence of either link pulses (10 Mbps PHY) or Idle symbols (100 Mbps PHY) and set its operating conditions accordingly ...
Page 115
... During 10 Mbps operation, LXT9785/LXT9785E encoded data is exchanged. When no data are being exchanged, the line is left in an idle state with NLPs transmitted to maintain link. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.2 Interface Descriptions TXENn TXDn_0 TPFOPn ...
Page 116
... RMII or SMII/SS-SMII on all eight ports. Refer to Note: The BGA15 package does not support the RMII interface. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers MDIX MDIX Mode 0 MDI forced 1 ...
Page 117
... Mbps mode. Use the above two-step process to eliminate the auto-negotiation BLT timer requirement. Figure 8 Internal Loopback ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ModeSel1 ModeSel0 ...
Page 118
... TxCLK, TxSYNC, RxCLK, and RxSYNC. The transmit TxCLK and TxSYNC are sourced from the MAC to the PHY and referenced to the REFCLK input. The receive RxCLK and RxSYNC are sourced by the PHY to the MAC and in reference to the REFCLK. ...
Page 119
... Specific bits in the registers are referenced using an “X.Y” notation, where X is the register number (0-32) and Y is the bit number (0-15). The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this interface is controlled by the MDDIS input pin. When MDDIS is High, all the MDIOs are completely disabled ...
Page 120
... Port Address Scheme 4.3.8 MII Sectionalization When sectionalized into two quad sections, the MDIO bus splits into two separate PHY access ports. Ports 0-3 of the MDIO section operate independently of ports 4-7. The MII isolate function is unaffected and operates normally. Sectionalization is selected by pulling ...
Page 121
... RMII interface by setting the initial fill FIFO Register bits 18.15:14 to 01. The FIFO setting bits should be set to 10 for the SMII interfaces. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers AND OR AND Interrupt Enable Section 4 ...
Page 122
... The LXT9785/LXT9785E provides a 12.5 MHz output pulse synchronous with the RxDatan outputs. See ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 34 on page 165. The power supplies should Table 57, Required Clock Characteristics, on page 172 Figure 22 on page Figure 23 on page 137 ...
Page 123
... When the network link is forced to a specific configuration, the LXT9785/LXT9785E immediately begins operating the network interface as commanded. When auto- negotiation is enabled, the LXT9785/LXT9785E begins the auto-negotiation/ parallel- detection operation. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 13 on page 124. 4.5 Initialization Page 123 ...
Page 124
... The recovery times are specified in Table 81, Power-Up Timing Parameters, on page 190 ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Power-up or Reset Read H/W Control Interface Initialize MDIO Registers Hardware Control ...
Page 125
... Cortina recommends that a minimum recovery time be allowed after bringing up a port from software or hardware reset. The recovery times are specified in Timing Parameters, on page 190 ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 84, Control Register (Address 0), on page 4.5 Initialization 192). During for pin ...
Page 126
... Next Pages. A special mode has been added to make manual next page exchange easier for software. When Register 6 “page” ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers CFG Resulting Register Bit Values 1 ...
Page 127
... Integrity Test Function State Diagram and in Section 28.3.4 State Diagrams, Figure 28-17-NLP Receive Link Integrity Test State Diagram. These diagrams illustrate that while the PHY is in the Link Test Fail Extend state, the last state before Link Pass state) Packet receive activity (RD) and Transmit Activity (DO) must be idle (RD = idle * D0 = idle) for link to establish ...
Page 128
... The LXT9785/LXT9785E exchanges transmit and receive data with the controller via the Serial MII (SMII). The SMII performs the following functions: • Conveys complete MII information between a 10/100 PHY and MAC with two pins per port. • Allows a multi-port MAC/PHY communication with one system clock. ...
Page 129
... PHY 1. Refer to Table 7, SMII Specific Signal Descriptions – PQFP, on page 39 for detailed signal descriptions. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers From Purpose Transmit data & control Synchronization Receive data & control Synchronization 4.7 Serial MII Operation ...
Page 130
... Revision 11.0 16 April 2007 Figure 15 Typical SMII Interface 125 MHz Sourced Externally or from Switch ASIC ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.7 Serial MII Operation Typical SMII Interface in a 16-Port System SECTION 8 TxDatan SYNC0 8 ...
Page 131
... Revision 11.0 16 April 2007 Figure 16 Typical SMII Quad Sectionalization 125 MHz Sourced Externally or from Switch ASIC ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.7 Serial MII Operation Typical SMII Interface in a 24-Port System RefClk0 RefClk1 8 TxDatan SYNC0 ...
Page 132
... SMII Reference Clock The REFCLK operates at 125 MHz. The transmit and receive data and control streams must always be synchronized to the REFCLK by the MAC and PHY. The LXT9785/ LXT9785E samples these signals on the rising edge of the REFCLK. 4.7.2 TxSYNC Pulse (SMII/SS-SMII) The TxSYNC pulse delimits segment boundaries and synchronizes with REFCLK ...
Page 133
... COL conditions using CRS and TxEN. CRS is unaffected by the transmit path. Figure 19 Serial MII Receive Synchronization CLOCK RxSYNC RX CRS ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 134. Status bit RxData<5> indicates the validity of the upper RXD0 RXD1 RXD2 RXD3 RXD4 RX_DV RXER ...
Page 134
... Source Synchronous-Serial Media Independent Interface Some system designs require the PHY to be placed between inches away from the MAC. A new Source Synchronous-Serial Media Independent Interface (SS-SMII) definition has been added because of this requirement. To provide a source synchronous interface between the PHY and MAC, the PHY must drive the RxCLK and the RxSYNC signals to the MAC ...
Page 135
... Revision 11.0 16 April 2007 Figure 20 Typical SS-SMII Interface 125 MHz Sourced Externally or from Switch ASIC ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.7 Serial MII Operation Typical SS-SMII Interface in a 16-Port System SECTION 8 TxData n TxSYNC0 ...
Page 136
... Revision 11.0 16 April 2007 Figure 21 Typical SS-SMII Quad Sectionalization 125 MHz Sourced Externally or from Switch ASIC ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.7 Serial MII Operation Typical SS-SMII Interface in a 24-Port System RefClk0 RefClk1 8 TxData n TxSYNC0 ...
Page 137
... The LXT9785/LXT9785E requires a 50 MHz reference clock (REFCLK). The device samples the RMII input signals on the rising edge of REFCLK and drives RMII output signals on the falling edge. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers TXER TXEN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 ...
Page 138
... RMII Data Flow Reduced MII Mode Data Flow Parallel to Serial Serial to di-bit Parallel pairs ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 46 on page 142 4B/5B 4-bit 5-bit nibbles symbols 4.8 RMII Operation Figure 24 shows shows 4B/ ...
Page 139
... Datasheet 249241, Revision 11.0 16 April 2007 Figure 25 Typical RMII Interface 50 Mhz Sourced Externally or from Switch ASIC ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.8 RMII Operation Typical RMII Interface in a 16-Port System SECTION 8 TxD0n 8 TxD1n 8 TxENn ...
Page 140
... LXT9785/LXT9785E Datasheet 249241, Revision 11.0 16 April 2007 Figure 26 Typical RMII Quad Sectionalization 50 MHz Sourced Externally or from Switch ASIC ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Typical RMII Interface in a 24-Port System RefClk0 RefClk1 8 TxD0n 8 TxD1n 8 TxENn ...
Page 141
... PCS Sublayer The Physical Coding Sublayer (PCS) provides the RMII interface, as well as the 4B/5B encoding/decoding function. For 100BASE-TX and 100BASE-FX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as long as TxEN is de-asserted. For 10T operation, the PCS layer merely provides a bus interface and serialization/de- serialization function. 10T operation does not use the 4B/5B encoder. ® ...
Page 142
... The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/. 3. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T /H/ (Error) code group is used to signal an error condition. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers MII Interface LXT9785 Encoder/Decoder Serializer/De-serializer ...
Page 143
... This provides a robust link, filtering out any small noise hits that may otherwise disrupt the link. Furthermore, 100 Mbps idle patterns will not bring Mbps link. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.9 100 Mbps Operation 5B Code Name ...
Page 144
... RxData outputs zeros until the received data are decoded and available for transfer to the controller. 4.9.3.6 Twisted-Pair PMD Sublayer The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and descrambling, line coding and decoding (MLT-3 for 100BASE-TX, Manchester for 10T), as well as receiving, polarity correction, and baseline wander correction functions. 4.9.3.6.1 ...
Page 145
... When Register bit 16 transmission of the far end fault code is enabled. The LXT9785/LXT9785E transmits far end fault code if fault conditions are detected by the Signal Detect pins. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.9 100 Mbps Operation Page 145 ...
Page 146
... Once link pulses are detected, data transmission is enabled and remains enabled as long as either the link pulses or data transmission continue. If link pulses stop, the data transmission is disabled. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.10 10 Mbps Operation Page 146 ...
Page 147
... IP phone. IP telephone system connection. Figure 29 Typical IP Telephone System Connection Power cable Power Outlet UPS/ Generator ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.11 DTE Discovery Process Figure 29 VoIP-Enabled Switch SD ProCurve Swi tch J4122B 1 0/100Base-T Ports Sta ...
Page 148
... LXT9785E device. However, control of the power supply and overall system control reside in the system processor. The processor communicates with the power supply unit (PSU) and switches it on and off dependant on the data that is supplied by the PHY. The PHY register data is read by the MAC using the MDIO interface. The required control bits are ...
Page 149
... Register bit 27 when a port search for a DTE requiring power is desired. Once set, Register bit 27.6 remains = 1 until the MAC clears it, either by directly clearing resetting the PHY. This allows the discovery process to continue to function if unsuccessful in detecting a DTE, without being continually re-enabled by the MAC. If Register bit 27 ...
Page 150
... These values are loaded with randomly created data from an internal LSFR that is free running and seeded with the PHY address of the LXT9785E port. The Next Pages are hard coded in the logic (the LXT9785E ignores any data written into Register 7) and are outlined in receiver monitors the next pages to determine that the exact next page data (especially the random data) transmitted is received ...
Page 151
... Discovery process transmits one last null page with the next page bit cleared to stop the DTE Discovery process. If each page is successfully auto-negotiated (it matches the transmitted page), DTE Discovery completes as previously described. The five Next Pages consist of a message page and four user pages. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ...
Page 152
... Determine Compatibility Options Nonmatching DTE Discovery NP Received Compatibility Transmit Last Page Continuously ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers LXT9785E Negotiation Flow Chart Start Auto-Negotiation/Forced Speed Set by Pins Power Up Advertisement Requirements Set by Pins or Link Down 1 and Dis_EN 27 Link Down 1 ...
Page 153
... Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.12 Monitoring Operations Table 85, Status Register (Address 1), on Table 94, Quick Status Register (Address 17, Hex ...
Page 154
... IPG. A software-selectable bit enables the RMII out-of-band signaling feature. Once this bit is set, the LXT9785/LXT9785E replaces the zeros with selected status bits during the IPG. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.12 Monitoring Operations stretch stretch Figure 31 on ...
Page 155
... The IDCODE instruction is always invoked after the state machine resets. The decode logic ensures the correct data flow to the Data registers according to the current instruction. Valid instructions are listed in ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers data data data data ...
Page 156
... The cable tests produce undefined results if the link partner is transmitting signals. Implementation methods may vary depending upon the system use requirements of Cable Diagnostics. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Description Capture Shift Update ...
Page 157
... April 2007 4.13.2 Operation Cable Diagnostics utilizes the PHY transmit drivers and receivers to test a single twisted- pair. A transmit pulse is driven down the twisted-pair under test and the reflected signal is analyzed. Link partners transmitting NLP, FLP, MLT3, or other TDR pulses may interfere with the ability of the LXT9785/LXT9785E to properly analyze the reflected Cable Diagnostic pulse ...
Page 158
... Register bits 29.12:11 are cleared when read and are cleared during the same read cycle when Register bit 29.9 is read, indicating a fault condition exists. 7. Normal PHY operation can be resumed by writing 0x4000h to Register software or hardware reset. The test suite can be run again by resuming at step 2 above. ...
Page 159
... The hardware enabled Link Hold-Off is controlled by the LINKHOLD pin. Internal pull- down resistors hold the pin in the inactive state. Connecting a 5k pull-up resistor to the pin enables the feature at power-up reset or external hardware pin Reset. Once a PHY port is programmed as desired, clearing Register bit 0.11 will re-enable that port. Each port must be individually re-enabled ...
Page 160
... Program the PHY to the desired configuration. 3. Clear Register bit 0.11 (power-down) to disable Link Hold-Off. 4. Normal operation resumes. Note: High is defined by the IO voltage supply level selected (2.5V or 3.3V). ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.14 Link Hold-Off Overview Page 160 ...
Page 161
... Bit Error Rate (BER), and long-line-length performance. To achieve maximum performance from the LXT9785/LXT9785E, attention to detail and good design practices are required. Refer to the Cortina Systems 8-Port 10/100 Mbps PHY Transceivers Design and Layout Guide application note for detailed design and layout information. 5.2 ...
Page 162
... Great care needs to be taken when laying out the power and ground planes. • Follow the guidelines in the Cortina Systems 8-Port 10/100 Mbps PHY Transceivers Design and Layout Guide for locating the split between the digital and analog VCC planes. • Keep the digital VCC plane away from the TPFOP/N and TPFIP/N signals, the magnetics, and the RJ-45 connectors. • ...
Page 163
... LXT9785/LXT9785E. See the 100BASE-FX Fiber Optic Transceivers-Connecting a PECL/LVPECL Interface Application Note (document number 250781) for detailed information on fiber interface designs and recommendations for Cortina PHYs. The following should occur in 3.3 V fiber transceiver applications as shown in • The transmit pair should be AC-coupled with 2.5 V supplies and re-biased to 3.3 V LVPECL levels • ...
Page 164
... V rail eases LED component selection by allowing more common, high-forward voltage LEDs to be used. Refer to Figure 33 LED Circuit ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 38. shows the interface circuitry for the logic translator. Figure 33 for a circuit illustration. ...
Page 165
... GNDD VCCIO VCCPECL GNDPECL ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers show typical application circuits for the Figure 38 on page 169 shows the interface circuitry for the logic 0.01μF Analog Supply Plane Digital Supply Plane 0.01 μ ...
Page 166
... LXT9785/9785E 1. The 100 Ω transmit load termination resistor typically required is integrated in the LXT9785/ LXT9785E. 2. The 100 Ω receive load termination resistor typically required is integrated in the LXT9785/ ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1:1 1 TPFIP 1:1 2 TPFIN .01 μ ...
Page 167
... TPFINn TPFIPn SD_2P5V GNDPECL VCCPECL 1. Refer to the transceiver manufacturers’ recommendations for termination circuitry. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers +3.3V +2.5V 0.01μF 0.01μF 1.4kΩ 27Ω − 0.1μF − 0.1μF 50Ω ...
Page 168
... SD_2P5V GNDPECL VCCPECL 1. Refer to the transceiver manufacturers’ recommendations for termination circuitry. 2. See Figure 38 on page 169 ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers +5V +2.5V 0.01μF 27Ω − 0.1μF 1.15kΩ 1.1kΩ 50Ω ...
Page 169
... Revision 11.0 16 April 2007 Figure 38 ON Semiconductor Triple PECL-to-LVPECL Translator 0.01 μF 5V 82Ω PECL Input Signal (5V Fiber Txcvr) 130Ω ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 5.3 Typical Application Circuits 5V 3.3V ON Semiconductor* 1 Vcc Vcc ...
Page 170
... Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Voltages with respect to ground unless otherwise specified. 3. Values are aggregated for all eight ports. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers and Figure 39 through Figure 62 represent the target ...
Page 171
... Output Low voltage (LED pins) Output High voltage 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Typ1 Sym Min (2 – ...
Page 172
... Parameter is guaranteed by design; not subject to production testing. 2. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Sym Min Typ1 Max V – ...
Page 173
... Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing percent into 100 Ω equivalent load of a typical fiber transceiver. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Sym Min Typ ...
Page 174
... MAU. 4. After line model specified by IEEE 802.3 for 10BASE-T MAU. Figure 39 SMII - 100BASE-TX Receive Timing REFCLK SYNC RxData TPFI ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1 Sym Min Typ Max Transmitter V 2.2 2.5 2.8 OP – ...
Page 175
... BT = 100 ns if using 10BASE- using 100BASE-TX or 100BASE-FX). Note: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill). ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Sym Min Typ1 Max Units t1 1.5 – ...
Page 176
... The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill). Figure 42 SMII - 100BASE-FX Transmit Timing REFCLK SYNC TxData TPFO ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ...
Page 177
... BT = 100 ns if using 10BASE- using 100BASE-TX or 100BASE-FX). Note: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill). ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Sym Min Typ1 Max t1 1.5 – ...
Page 178
... BT = 100 ns if using 10BASE- using 100BASE-TX or 100BASE-FX). Note: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill). ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Sym Min Typ1 Max Units 3 t4 – ...
Page 179
... BT = 100 ns if using 10BASE- using 100BASE-TX or 100BASE-FX). Note: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill). ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ...
Page 180
... The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill). Figure 47 SS-SMII - 100BASE-FX Receive Timing REFCLK RxCLK RxSYNC RxData TPFI ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ...
Page 181
... BT = 100 ns if using 10BASE- using 100BASE-TX or 100BASE-FX). Note: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill). ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Sym Min Typ1 Max Units t1 – ...
Page 182
... BT = 100 ns if using 10BASE- using 100BASE-TX or 100BASE-FX). Note: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill). ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ...
Page 183
... The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill). Figure 51 RMII - 100BASE-TX Receive Timing REFCLK RxData[1:0] TPFI CRS_DV ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ...
Page 184
... BT = 100 ns if using 10BASE- using 100BASE-TX or 100BASE-FX). Note: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill). ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Sym Min Typ1 ...
Page 185
... The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill). Figure 54 RMII - 100BASE-FX Transmit Timing REFCLK TxData(1:0) TPFO TxEN ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Sym Min Typ1 ...
Page 186
... Values and conditions from RMII Specification, Rev. 1.2. Note: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill). ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Sym Min Typ1 t1 4 ...
Page 187
... The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a Note: default configuration of 00 (32 bits of initial fill). Figure 57 Auto-Negotiation and Fast Link Pulse Timing Clock Pulse TPFOP ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ...
Page 188
... Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Figure 59 MDIO Write Timing (MDIO Sourced by MAC) MDC MDIO ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers t4 t5 Sym Min Typ1 Max t1 – ...
Page 189
... MDC to MDIO output delay, sourced by PHY 1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing. Figure 61 Power-Up Timing ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers t3 Sym Min Typ1 Max t1 10 – ...
Page 190
... Reset pulse width Reset recovery delay 1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Sym Min Typ1 Max Units v1 2 ...
Page 191
... Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer and Media Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps Auto-Negotiation” sections of the IEEE 802.3 standard. Additional registers (16 through 21, 25, 27, and 29) are defined in accordance with the IEEE 802 ...
Page 192
... Link Status is reported in 10 Mbps mode as down and in 100 Mbps mode loopback mode. Register bits 17.12 (Receive Status) and 17.13 (Transmit Status) are not updated in 10 Mbps loopback mode. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Description 0 = Normal operation 1 = PHY reset 0 = Disable loopback mode ...
Page 193
... PHY able to perform half-duplex 100BASE PHY not able to operate at 10 Mbps in full-duplex mode 1 = PHY able to operate at 10 Mbps in full-duplex mode 0 = PHY not able to operate at 10 Mbps in half-duplex 1 = PHY able to operate at 10 Mbps in half-duplex mode 0 = PHY not able to perform full-duplex 100BASE- PHY able to perform full-duplex 100BASE-T2 ...
Page 194
... Link Jabber condition not detected 1 = Jabber condition detected 0 = Basic register capabilities 1 = Extended register capabilities Description The PHY identifier composed of bits 3 through 18 of the OUI Description The PHY identifier composed of bits 19 through 24 of the OUI 6 bits containing manufacturer’s part number 3 bits containing manufacturer’s revision number ...
Page 195
... If Register bit 4.13 is set to advertise a fault, Register bit 1.4 will be set. Register bit 4.13 is set or cleared only through the MDC/MDIO interface and is not cleared upon completion of auto-negotiation. Note: Restart the auto-negotiation process whenever Register 4 is written/modified. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ...
Page 196
... Pause Read Only 2. Default value at the start of auto-negotiation code word transmission. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Description 0 = 100BASE-T4 capability is not available 1 = 100BASE-T4 capability is available (The LXT9785/LXT9785E does not support 100BASE-T4 but allows this bit to be set to advertise in the auto-negotiation sequence for 100BASE-T4 operation ...
Page 197
... A/N Able Read Only Latching High – cleared when read ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Description 0 = Link partner is not Pause capable 1 = Link partner can send and receive Pause 0 = Link partner is not 100BASE-T4 capable 1 = Link partner is 100BASE-T4 capable ...
Page 198
... Unformatted Code Field Read Only 2. Default value at the start of auto-negotiation code word transmission. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Description 0 = Last page 1 = Additional next pages follow Write as 0, ignore on Read Unformatted page 1 = Message page ...
Page 199
... The BGA15 package does not support fiber. Default for the BGA15 package means the bits do not have a default value and may initially contain any value. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Description Write as 0, ignore on Read 0 = Normal operation ...
Page 200
... Default values are set by the hardware configuration PAUSE pin. The BGA15 package does not have a Pause hardware configuration pin. The default for the BGA15 package is 0. ® Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Description Write as 0, ignore on Read Select twisted-pair mode for this port 1 = Select fiber mode for this port Write as '0', ignore on Read (BGA15) ...