PX1011B-EL1/N NXP Semiconductors, PX1011B-EL1/N Datasheet - Page 2

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PX1011B-EL1/N

Manufacturer Part Number
PX1011B-EL1/N
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PX1011B-EL1/N

Lead Free Status / RoHS Status
Not Compliant

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Quantity
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NXP Semiconductors
3. Quick reference data
PX1011B_4
Product data sheet
2.3 JTAG interface
2.4 Power management
2.5 Clock
2.6 Miscellaneous
I
I
I
I
I
I
I
I
I
I
I
Table 1.
Symbol Parameter
V
V
V
V
V
V
f
T
clk(ref)
amb
DDD1
DDD2
DDD3
DD
DDA1
DDA2
JTAG (IEEE 1149.1) boundary scan interface
Built-In Self Test (BIST) controller tests SerDes and I/O blocks at speed
3.3 V CMOS signaling
Dissipates < 300 mW in L0 normal mode
Support power management of L0, L0s and L1
100 MHz external reference clock with 300 ppm tolerance
Supports spread spectrum clock to reduce EMI
On-chip reference clock termination
LFBGA81 leaded or lead-free packages
Operating ambient temperature
ESD protection voltage for Human Body Model (HBM): 2000 V
N
N
Commercial: 0 C to +70 C
Industrial: 40 C to +85 C
digital supply voltage 1
digital supply voltage 2
digital supply voltage 3
supply voltage
analog supply voltage 1
analog supply voltage 2
reference clock frequency
ambient temperature
Quick reference data
Rev. 04 — 4 September 2009
Conditions
for JTAG I/O
for SSTL_2 I/O
for core
for high-speed
serial I/O and PVT
for serializer
for serializer
operating
commercial
industrial
PCI Express stand-alone X1 PHY
Min
3.0
2.3
1.15
1.15
1.15
3.0
99.97
0
40
Typ
3.3
2.5
1.2
1.2
1.2
3.3
100
-
-
PX1011B
© NXP B.V. 2009. All rights reserved.
Max
3.6
2.7
1.3
1.3
1.3
3.6
100.03
+70
+85
Unit
V
V
V
V
V
V
MHz
2 of 30
C
C

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