CY7B933-JC Cypress Semiconductor Corp, CY7B933-JC Datasheet - Page 7

• Manufacturer Part Number: CY7B933-JC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7B933-JC

• Lead Free Status / RoHS Status: Not Compliant

Table 2. CY7B933 HOTLink Receiver
Document #: 38-02017 Rev. *H
Q
(Q
SC/D (Q
RVS (Q
RDY
CKR
A/B
INA
INB
(INB+)
SI
(INB)
SO
RF
REFCLK
MODE
Name
07
b  h
)
j
a
)
)
TTL Out
TTL Out
TTL Out
TTL Out
TTL Out
PECL in
Diff In
PECL in
(Diff In)
PECL in
(Diff In)
TTL Out
TTL In
TTL In
Three-
Level In
I/O
Q
nously with CKR. When MODE is HIGH, Q
Special character/data select. SC/D indicates the context of received data. HIGH indicates a Control
(Special Character) code, LOW indicates a Data character. When MODE is HIGH (placing the receiver
in Unencoded mode), SC/D acts as the Q
Received violation symbol. A HIGH on RVS indicates that a code rule violation has been detected in the
received data stream. A LOW shows that no error has been detected. In BIST mode, a LOW on RVS
indicates correct operation of the Transmitter, Receiver, and link on a byte-by-byte basis. When MODE
is HIGH (placing the receiver in Unencoded mode), RVS acts as the Q
as Q
Data output ready. A LOW pulse on RDY indicates that new data has been received and is ready to be
delivered. A missing pulse on RDY shows that the received data is the Null character (normally inserted
by the transmitter as a pad between data inputs). In BIST mode RDY will remain LOW for all but the last
byte of a test loop and will pulse HIGH one byte time per BIST loop.
Clock read. This byte rate clock output is phase and frequency aligned to the incoming serial data stream.
RDY, Q
Serial data input select. This PECL 100K (+5V referenced) input selects INA or INB as the active data
input. If A/B is HIGH, INA is connected to the shifter and signals connected to INA will be decoded. If A/B
is LOW INB is selected.
Serial data input A. The differential signal at the receiver end of the communication link may be connected
to the differential input pairs INA or INB. Either the INA pair or the INB pair can be used as the main
data input and the other can be used as a loopback channel or as an alternative data input selected by
the state of A/B. One input of an intentionally unused differential-pair (INA or INBshould be terminated
to V
Serial data input B. This pin is either a single-ended PECL data receiver (INB) or half of the INB differential
pair. If SO is wired to V
If SO is normally connected and loaded, INB becomes a single-ended PECL 100K (+5 V referenced)
serial data input. INB is used as the test clock while in Test mode.
Status input. This pin is either a single-ended PECL status monitor input (SI) or half of the INB differential
pair. If SO is wired to V
If SO is normally connected and loaded, SI becomes a single-ended PECL 100K (+5V referenced) status
monitor input, which is translated into a TTL-level signal at the SO pin.
Status out. SO is the TTL-translated output of SI. It is typically used to translate the carrier detect output
from a fiber-optic receiver connected to SI. When this pin is normally connected and loaded (without any
external pull-up resistor), SO will assume the same logical level as SI and INB will become a single-ended
PECL serial data input. If the status monitor translation is not desired, then SO may be wired to V
the INB pair may be used as a differential serial data input.
Reframe enable. RF controls the Framer logic in the Receiver. When RF is held HIGH, each SYNC (K28.5)
symbol detected in the shifter will frame the data that follows. If it is HIGH for 2,048 consecutive bytes,
the internal framer switches to double-byte mode. When RF is held LOW, the reframing logic is disabled.
The incoming data stream is then continuously deserialized and decoded using byte boundaries set by
the internal byte counter. Bit errors in the data stream will not cause alias SYNC characters to reframe
the data erroneously.
Reference clock. REFCLK is the clock frequency reference for the clock/data synchronizing PLL.
REFCLK sets the approximate center frequency for the internal PLL to track the incoming bit stream.
REFCLK must be connected to a crystal-controlled time base that runs within the frequency limits of the
Tx/Rx pair, and the frequency must be the same as the transmitter CKW frequency (within CKW  0.1%).
Decoder mode select. The level on the MODE pin determines the decoding method to be used. When
wired to GND, MODE selects 8B/10B decoding. When wired to V
the decoder and are sent to Q
the internal bit clock generator is disabled and INB becomes the bit rate test clock to be used for factory
test. In typical applications, MODE is wired to V
Description
0–7
CC
07
parallel data output. Q
.
through a 15-K resistor to assure that no data transitions are accidentally created.
07
, SC/D, and RVS all switch synchronously with the rising edge of this output.
CC
CC
, then INB can be used as differential line receiver interchangeably with INA.
, then INB can be used as differential line receiver interchangeably with INA.
0–7
aj
contain the most recently received data. These outputs change synchro-
directly. When left floating (internal resistors hold the MODE pin at V
a
0, 1, ...7
output. SC/D has the same timing as Q
CC
become Q
or GND.
b, c,...h
CC
, respectively.
, registered shifter contents bypass
CY7B923, CY7B933
j
output. RVS has the same timing
07
.
Page 7 of 40
CC
CC
and
/2)
[+] Feedback