CY7B933-JI Cypress Semiconductor Corp, CY7B933-JI Datasheet - Page 12

• Manufacturer Part Number: CY7B933-JI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7B933-JI

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02017 Rev. *E
BIST mode is intended to check the entire function of the
Transmitter (except the Transmitter input pins and the bypass
function in the Encoder), the serial link, and the Receiver. It
augments normal factory ATE testing and provides the
designer with a rigorous test mechanism to check the link
transmission system without requiring any significant system
overhead.
While in Bypass mode, the BIST logic will function in the same
way as in the Encoded mode. MODE = HIGH and
BISTEN = LOW causes the Transmitter to switch to Encoded
mode and begin sending the BIST pattern, as if MODE = LOW.
When BISTEN returns to HIGH, the Transmitter resumes
normal Bypass operation. In Test mode the BIST function
works as in the Normal mode. For more information on BIST,
consult the “HOTLink Built-In Self-Test” application note.
Test Mode
The MODE input pin selects between three transmitter
functional modes. When wired to V
the Encoder and load directly from the Input register into the
Shifter. When wired to GND, the inputs D
are encoded using the Fibre Channel 8B/10B codes and
sequences (shown at the end of this datasheet). Since the
Transmitter is usually hard wired to Encoded or Bypass mode
and not switched between them, a third function is provided for
the MODE pin. Test mode is selected by floating the MODE
pin (internal resistors hold the MODE pin at V
is used for factory or incoming device test.
Test mode causes the Transmitter to function in its Encoded
mode, but with OutA+/OutB+ (used as a differential test clock
input) as the bit rate clock input instead of the internal
PLL-generated bit clock. In this mode, inputs are clocked by
CKW and transfers between the Input register and Shifter are
timed by the internal counters. The bit-clock and CKW must
maintain a fixed phase and divide-by-ten ratio. The phase and
pulse width of RP are controlled by phases of the bit counter
(PLL feedback counter) as in Normal mode. Input and output
patterns can be synchronized with internal logic by observing
the state of RP or the device can be initialized to match an ATE
test pattern using the following technique:
Test mode is intended to allow logical, DC, and AC testing of
the Transmitter without requiring that the tester check output
data patterns at the bit rate, or accommodate the PLL lock,
tracking, and frequency range characteristics that are required
when the HOTLink part operates in its normal mode. To use
OutA+/OutB+ as the test clock input, the FOTO input is held
HIGH while in Test mode. This forces the two outputs to go to
an “PECL LOW,” which can be ignored while the test system
creates a differential input signal at some higher voltage.
CY7B933 HOTLink Receiver Operating Mode
Description
In normal user operation, the Receiver can operate in either of
two modes. The Encoded mode allows a user system to send
1. With the MODE pin either HIGH or LOW, stop CKW and
2. Force the MODE pin to MID (open or V
3. Start the bit-clock and let it run for at least two cycles.
4. Start the CKW clock at the bit-clock/10 rate.
bit-clock.
clocks are stopped.
CC
, the D(
0–7
CC
a–j
, SVS, and SC/D
CC
/2) while the
) inputs bypass
/2). Test mode
and receive eight-bit data and control information without first
converting it to transmission characters. The Bypass mode is
used for systems in which the encoding and decoding is
performed by an external protocol controller.
In either mode, serial data is received at one of the differential
line receiver inputs and routed to the Shifter and the Clock
Synchronization. The PLL in the Clock Synchronizer aligns the
internally generated bit rate clock with the incoming data
stream and clocks the data into the shifter. At the end of a byte
time (ten bit times), the data accumulated in the shifter is trans-
ferred to the Decode register.
To properly align the incoming bit stream to the intended byte
boundaries, the bit counter in the Clock Synchronizer must be
initialized. The Framer logic block checks the incoming bit
stream for the unique pattern that defines the byte boundaries.
This combinatorial logic filter looks for the X3.230 symbol
defined as “Special Character Comma” (K28.5). Once K28.5
is found, the free running bit counter in the Clock Synchronizer
block is synchronously reset to its initial state, thus “framing”
the data to the correct byte boundaries.
Since noise-induced errors can cause the incoming data to be
corrupted, and since many combinations of error and legal
data can create an alias K28.5, an option is included to disable
resynchronization of the bit counter. The Framer will be
inhibited when the RF input is held LOW. When RF rises, RDY
will be inhibited until a K28.5 has been detected, and RDY will
resume its normal function. Data will continue to flow through
the Receiver while RDY is inhibited.
Encoded Mode Operation
In Encoded mode the serial input data is decoded into eight
bits of data (Q
diagnostic output bit (RVS). If the pattern in the Decode
register is found in the Valid Data Characters table, the context
of the data is decoded as normal message data and the SC/D
output will be LOW. If the incoming bit pattern is found in the
Valid Special Character Codes and Sequences table, it is inter-
preted as “control” or “protocol information,” and the SC/D
output will be HIGH. Special characters include all protocol
characters defined for use in packets for Fibre Channel,
ESCON, and other proprietary and diagnostic purposes.
The Violation symbol that can be explicitly sent as part of a
user data packet (i.e., Transmitter sending C0.7; D
00000 and SC/D = 1; or SVS = 1) will be decoded and
indicated in exactly the same way as a noise-induced error in
the transmission link. This function will allow system
diagnostics to evaluate the error in an unambiguous manner,
and will not require any modification to the receiver data
interface for error-testing purposes.
Bypass Mode Operation
In Bypass mode the serial input data is not decoded, and is
transferred directly from the Decode register to the Output
register’s 10 bits (Q(
preencoded prior to transmission, and will be decoded in
subsequent logic external to HOTLink. This data can use any
encoding method suitable to the designer. The only restrictions
upon the data encoding method is that it contain suitable
transition density for the Receiver PLL data synchronizer (one
per 10-bit byte) and that it be compatible with the transmission
media.
0
–Q
7
), a context control bit (SC/D), and a system
a–j
). It is assumed that the data has been
CY7B923
CY7B933
Page 12 of 33
7–0
= 111