PEB3265FV15XT Lantiq, PEB3265FV15XT Datasheet - Page 138

• Manufacturer Part Number: PEB3265FV15XT
• Manufacturer: Lantiq

Specifications of PEB3265FV15XT

• On-hook Transmission: Yes
• Polarity Reversal: Yes
• On-chip Ring Relay Driver: Yes
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TQFP
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Lead Free Status / RoHS Status: Compliant

Preliminary
5
The DuSLIC connects the analog subscriber to the digital switching network by two
different types of digital interfaces to allow for the highest degree of flexibility in different
applications:
• PCM interface combined with a serial microcontroller interface
• IOM-2 interface.
The PCM/IOM-2 pin selects the interface mode.
PCM/IOM-2 = 0: The IOM-2 interface is selected.
PCM/IOM-2 = 1: The PCM/ C interface is selected.
The analog TIP/RING interface connects the DuSLIC to the subscriber.
5.1
In PCM/ C interface mode, voice and control data are separated and handled by
different pins of the SLICOFI-2x. Voice data are transferred via the PCM highways while
control data are using the microcontroller interface.
5.1.1
The serial PCM interface is used to transfer A-law or -law-compressed voice data. In
test mode, the PCM interface can also transfer linear data. The eight pins of the PCM
interface are used as follows (two PCM highways):
PCLK:
FSC:
DRA:
DRB:
DXA:
DXB:
TCA:
TCB:
The FSC pulse identifies the beginning of a receive and transmit frame for both
channels. The PCLK clock signal synchronizes the data transfer on the DXA (DXB) and
DRA (DRB) lines. On all channels, bytes are serialized with MSB first. As a default
setting, the rising edge indicates the start of the bit, while the falling edge is used to buffer
the contents of the received data on DRA (DRB). If double clock rate is selected (PCLK
Data Sheet
Interfaces
PCM Interface with a Serial Microcontroller Interface
PCM Interface
PCM Clock, 128 kHz to 8192 kHz
Frame Synchronization Clock, 8 kHz
Receive Data Input for PCM Highway A
Receive Data Input for PCM Highway B
Transmit Data Output for PCM Highway A
Transmit Data Output for PCM Highway B
Transmit Control Output for PCM Highway A, Active low during
transmission
Transmit Control Output for PCM Highway B, Active low during
transmission
138
Interfaces
2000-07-14
DuSLIC