SI3202-G-GSR Silicon Laboratories Inc, SI3202-G-GSR Datasheet
SI3202-G-GSR
Specifications of SI3202-G-GSR
Related parts for SI3202-G-GSR
SI3202-G-GSR Summary of contents
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... PCM/SPI or GCI bus digital interfaces. The Si3200/2 linefeed ICs perform all high-voltage functions and operate from a 3 supply as well as single or dual battery supplies up to 100 V (Si3200) or 125 V (Si3202). The Si3220 and Si3225 are available in a 64-pin thin quad flat package (TQFP), and the Si3200/2 is available in a thermally-enhanced 16-pin small outline (SOIC) package ...
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Si3220/25 Si3200/02 2 Rev. 1.3 ...
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... Pin Descriptions: Si3220/ 101 5. Pin Descriptions: Si3200 105 6. Package Outline: 64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 7. Package Outline: 16-Pin ESOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8. Silicon Labs Si3220/25 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9. Dual ProSLIC Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 Si3220/25 Si3200/02 Rev. 1.3 Page ...
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... On Si3200 revision E, the dv/dt of the voltage applied to the V 4. Operation of the Si3220/Si3225 above 125 °C junction temperature may degrade device reliability. The Si3200/Si3202 should be operated at a junction temperature below 140 °C for optimal reliability. ...
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... On Si3200 revision E, the dv/dt of the voltage applied to the V 4. Operation of the Si3220/Si3225 above 125 °C junction temperature may degrade device reliability. The Si3200/Si3202 should be operated at a junction temperature below 140 °C for optimal reliability. ...
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... Low Battery Supply Voltage, Si3200 High Battery Supply Voltage, Si3202 Low Battery Supply Voltage, Si3202 *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. ...
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Table 3. 3.3 V Power Supply Characteristics = = ( – °C for K/F-Grade, – °C for B/G-Grade) DD DD1 DD4 A Parameter Symbol V Supply Current I DD ...
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Si3220/25 Si3200/02 Table 3. 3.3 V Power Supply Characteristics = = ( – °C for K/F-Grade, – °C for B/G-Grade) DD DD1 DD4 A Parameter Symbol Chipset Power P ...
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Table Power Supply Characteristics = = ( – °C for K/F-Grade, – °C for B/G-Grade) DD DD1 DD4 A Parameter Symbol V – V Supply I ...
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Si3220/25 Si3200/02 Table Power Supply Characteristics = = ( – °C for K/F-Grade, – °C for B/G-Grade) DD DD1 DD4 A Parameter Symbol V Supply Current ...
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... The level of any unwanted tones within the bandwidth kHz does not exceed –55 dBm. 7. The OBIAS and ABIAS registers program the dc bias current through the SLIC in the on-hook transmission and off- hook active conditions, respectively. This per-pin total current setting should be selected so it can accommodate the sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given application ...
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... The level of any unwanted tones within the bandwidth kHz does not exceed –55 dBm. 7. The OBIAS and ABIAS registers program the dc bias current through the SLIC in the on-hook transmission and off- hook active conditions, respectively. This per-pin total current setting should be selected so it can accommodate the sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given application ...
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Table 6. Linefeed Characteristics = ( – V 3. DD1 DD4 A Parameter Maximum Loop Resistance (adaptive 1 linefeed disabled ) Maximum Loop Resistance (adaptive 1 linefeed enabled ) DC Loop Current Accuracy ...
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Si3220/25 Si3200/02 Table 6. Linefeed Characteristics (Continued – V 3. DD1 DD4 A Parameter Loop Voltage Sense Accuracy Loop Current Sense Accuracy Power Alarm Threshold Accuracy Notes: 1. Adaptive linefeed is ...
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Table 8. Si3200/2 Characteristics = = (V 3. °C for K/F-Grade, – °C for B/G-Grade Parameter TIP/RING Pulldown Transistor Satura- tion Voltage TIP/RING Pullup Transistor Saturation Voltage Battery Switch ...
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Si3220/25 Si3200/02 Table 10. DC Characteristics ( – V 3. DD1 DD4 A Parameter Symbol High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage ...
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Table 12. Switching Characteristics—SPI ( – 3. DD1 DD4 A 1 Parameter 2 Cycle Time SCLK Rise Time, SCLK Fall Time, SCLK Delay Time, SCLK Fall to SDO Active Delay Time, ...
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Si3220/25 Si3200/02 Table 13. Switching Characteristics—PCM Highway Interface = ( – V 3. DD1 DD4 A Parameter PCLK Period Valid PCLK Inputs 2 FSYNC Period PCLK Duty Cycle Tolerance PCLK Period Jitter Tolerance ...
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PCLK FSYNC DRX DTX Figure 2. PCM Highway Interface Timing Diagram Si3220/25 Si3200/ ...
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Si3220/25 Si3200/02 Table 14. Switching Characteristics—GCI Highway Serial Interface = ( – V 3. DD1 DD4 A 1 Parameter PCLK Period (2.048 MHz PCLK Mode) PCLK Period (4.096 MHz PCLK Mode) 2 FSYNC ...
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PCLK t su1 FSYNC Frame 0, DRX Bit DTX Figure 4. GCI Highway Interface Timing Diagram (4.096 MHz PCLK Mode) Acceptable Region Figure 5. Transmit and Receive Path SNDR Si3220/25 Si3200/ ...
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Si3220/25 Si3200/02 Fundamental Output Power (dBm0) Figure 6. Overload Compression Performance 5 0 −5 −10 −15 −20 −25 −30 −35 −40 −45 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 ...
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5 0 −5 −10 −15 −20 −25 −30 −35 −40 −45 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1 ...
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Si3220/25 Si3200/02 1100 1000 900 800 700 600 500 400 300 200 100 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400 Figure 9. Transmit Group Delay Distortion 1100 1000 900 ...
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Si3220/25 Si3200/02 Rev. 1.3 25 ...
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Si3220/25 Si3200/02 26 Rev. 1.3 ...
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Si3220/25 Si3200/02 Rev. 1.3 27 ...
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... W, ±5% R24, R25 Notes: 1. Required for Si3200 revision E only. 2. R24 and R25 must be populated for each Si3220 in the system. Table 16. Si3220 + Si3202 External Component Values Component Value C1, C2, C11, C12 100 nF, 200 V, X7R, ±20% Filter capacitors for TIP, RING ac-sensing inputs. ...
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... Si3220/25 Si3200/02 Value TIP/RING compensation capacitors. Low-pass filter capacitors to stabilize differential and com- mon mode SLIC feedback loops. Decoupling for battery voltage supply pins. Decoupling for analog and digital chip supply pins. Sense resistors for TIP, RING dc sensing nodes. Sense resistors for battery voltage sensing nodes. ...
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... TQFP, and the Si3200/2 is available in a thermally-enhanced 16-lead SOIC. 3.1. Dual ProSLIC Architecture The Dual ProSLIC chipset is comprised of a low-voltage CMOS device that uses a low-cost integrated linefeed interface IC to control the high voltages needed for operating the terminal equipment connected to the telephone line ...
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Power Supply Sequencing Note: This section applies to Si3200 revision E only. To ensure proper operation, the following power sequencing guidelines should be followed: V should be allowed to reach its steady state DD voltage at least 20 ms ...
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... Control C AC TIP or RING Figure 15. Simplified Dual ProSLIC Linefeed Architecture for TIP and RING Leads (Diagram Illustrates either TIP or RING Lead of a Single Channel) 32 (STIPDCa/b and SRINGDCa/b) are placed on the SLIC side of any protection resistance placed in series with the TIP and RING leads. If line-side sensing is desired, ...
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Linefeed Operation States The linefeed interface includes eight different operating states as shown in Table 18. The linefeed register settings (LF[2:0], linefeed register) are also listed. The open state is the default condition in the absence of any pre-loaded ...
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Si3220/25 Si3200/02 Table 19. Register and RAM Locations for Linefeed Control Parameter Register/ Mnemonic Linefeed LINEFEED Linefeed Shadow LINEFEED Battery Feed Control RLYCON Loop Current Limit On-Hook Line Voltage Common Mode Voltage V Delta for Off-Hook VOCDELTA OC V Delta ...
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VOCDELTA kOhms Figure 16. Adaptive Linefeed V/I Behavior When the Si3220/Si3225 is used with the Si3200/2 linefeed device, the source impedance of the dc feed is 640 Ω before the ...
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Si3220/25 Si3200/02 transition point. In the case of the discrete bipolar linefeed, since the source impedance is 320 Ω both before and after the adaptive linefeed transition, the V/I curve exhibits no discontinuity at the transition points when VOCDELTA = ...
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... RING lead. RING Table 21 lists the register set associated with the loop monitoring functions. The Dual ProSLIC chipsets also include the ability to perform loop diagnostic functions as outlined in "3.32.2. Line Test and Diagnostics" on page 96. 3.8. Power Monitoring and Power Fault ...
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Si3220/25 Si3200/02 Table 21. Register and RAM Locations Used for Loop Monitoring Parameter Register/RAM Mnemonic Loop Voltage Sense VLOOP (V – TIP RING TIP Voltage Sense VTIP RING Voltage Sense VRING Loop Current Sense ILOOP Battery Voltage Sense ...
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Transistor Power Equations (Using Discrete Transistors) When using the Si3220 or Si3225 with discrete bipolar transistors possible to control the total power of the solution by individually regulating the power in each discrete transistor. Figure 18 illustrates ...
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... Refer to “AN55: Dual ProSLIC User Guide” for optimal thermal dissipation layout guidelines. The Dual ProSLIC chipset is designed with the ability to source long loop lengths in excess of 18 kft but can also accommodate short loop configurations. For example, the Si3220 can operate from one of two battery supplies depending on the operating state ...
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Table 22. Register and RAM Locations Used for Power Monitoring and Power Fault Detection Parameter Si3200/2 Total Power Output Monitor Si3200/2 Power Alarm Interrupt Pending Si3200/2 Power Alarm Interrupt Enable Q1/Q2 Power Alarm Threshold (discrete) Q1/Q2 Power Alarm Threshold (Si3200/2) ...
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... Si3220/25 Si3200/02 3.9. Automatic Dual Battery Switching The Dual ProSLIC chipsets provide the ability to switch between several user-provided battery supplies to aid thermal management. Two specific scenarios where this method may be required follow: Ringing to off-hook state transition (Si3220): During the on-hook operating state, the Dual ...
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Table 23. Register and RAM Locations Used for Battery Switching Parameter High Battery Detect Threshold Low Battery Detect Threshold Ringing Battery Switch (Si3220 only) Battery Select Indicator Battery Switching LPF *Note: Usable range for BATHTH and BATLTH is limited to ...
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... V (typically –48 V) and V (typically –24 V) rails BHI BLO V BRING V BLO V BHI Figure 20. 3-Battery Switching with Si3220/Si3200/Si3202 Table 24. Three-Battery Switching Components Component R101 R102 R103 44 using the switch internal to the Si3200/2. The Si3220’s GPO pin is used along with the external transistor circuit to switch the V onto the Si3200/2’ ...
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Loop Closure Detection Loop closure detection is required to accurately signal a terminal device going off-hook during the Active, On- Hook Transmission (forward or reverse polarity), and ringing linefeed states. The functional blocks required to implement a loop closure ...
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Si3220/25 Si3200/02 Table 25. Register and RAM Locations Used for Loop Closure Detection Parameter Register/RAM Loop Closure Interrupt Pending Loop Closure Interrupt Enable Linefeed Shadow Loop Closure Detect Status Loop Closure Detect Debounce Interval Loop Current Sense Loop Closure Threshold ...
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The output of the debounce filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the loop closure debounce interval, LONGDBI. If the debounce interval is satisfied, the ...
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Si3220/25 Si3200/02 Table 27. State Transitions During Ground Key Detection # Loop State 1 LOOP OPEN 2 RING-GND 3 RING-GND (FWD-ACTIVE) 4 LOOP CLOSURE (FWD-ACTIVE) 5 LOOP OPEN (FWD-ACTIVE Input LONG Signal I Processor Q5 ...
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Table 28. Register and RAM Locations Used for Ground Key Detection Register/ Parameter Mnemonics Ground Key Interrupt Pending IRQVEC2 Ground Key Interrupt Enable Ground Key Linefeed Shadow LINEFEED Ground Key Detect Status LCRRTP Ground Key Detect Debounce LONGDBI Interval Longitudinal ...
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... Adding significant dc offset also increases the power dissipation in the Si3200/2 and may require additional airflow or modified PCB layout to maintain acceptable operating temperatures in the line feed circuitry. The Dual ProSLIC chipset automatically applies and removes the ringing signal during V at the ...
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Table 29. Register and RAM Locations Used for Ringing Generation Parameter Register/RAM Mnemonic Ringing Waveform RINGCON Ringing Active Timer Enable RINGCON Ringing Inactive Timer RINGCON Enable Ringing Oscillator Enable RINGCON Monitor Ringing Oscillator Active RINGTALO/ Timer RINGTAHI Ringing Oscillator Inactive ...
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... Internal Trapezoidal Ringing In addition waveform, the Dual ProSLIC can generate a trapezoidal ringing waveform similar to the one illustrated in Figure 26. RINGPHAS RAM addresses are used for programming the ringing wave shape as follows: RINGPHAS = 4 x Period x 8000 RINGAMP = (Desired V/160 ...
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V RING Si3220 DC Offset GND V TIP DC Offset V OFF -80V V RING V BATR Figure 25. Internal Unbalanced Ringing To enable unbalanced ringing, set the RINGUNB bit of the RINGCON register. As with internal balanced ringing, the ...
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... By monitoring this path, the Dual ProSLIC detects a dc current flowing in the loop once the end equipment has gone off-hook. Table 30 provides recommended register and RAM settings for various applications, and Table 31 lists the register and ...
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... Ringtrip Timeout Counter The Dual ProSLIC incorporates a ringtrip timeout counter, RTCOUNT, that will monitor the status of the ringing control. When exiting ringing, the Dual ProSLIC will allow the ringtrip timeout counter a sufficient amount of time (RTCOUNT x 1.25 ms/LSB) for the mode to switch to On-hook Transmission or Active ...
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... Interval Loop Current Sense (monitor only) 3.15.3. Loop Closure Mask The Dual ProSLIC implements a loop closure mask to ensure mode change between ringing and active or on- hook transmission without causing an erroneous loop closure detection. The loop closure mask register, LCRMASK, should be set such that loop closure detection is ignored for the time (LCRMASK 1 ...
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... TRD2b are provided in all product versions, and ringing relay drivers RRDa and RRDb are included for the Si3225 only. In most applications, the relay can be driven directly from the Dual ProSLIC with no external relay drive circuitry required. Figure 28 illustrates the internal relay driver circuitry using relay. ...
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... Si3220/25 Si3200/02 Si3220/ Si3225 Figure 29. Driving Relays with V The maximum allowable R value can be calculated with the following equation: DRV MaxR DRV Table 32. Recommended R ProSLIC V Relay V DD 3.3 V ±5% 3.3 V ± ± ±5% 3.3 V ± ±5% 3.3 V ± ±10% 3.3 V ± ±10% 3.3 V ± ...
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Si3220/25 Si3200/02 Rev. 1.3 59 ...
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... OHT state or to the ACTIVE state in response to a linefeed state change. 3.17. Polarity Reversal The Dual ProSLIC devices support polarity reversal for message-waiting functionality and various signaling modes. The ramp rate can be programmed for a smooth transition or an abrupt transition to accommodate different application requirements ...
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Setting the linefeed register to the opposite polarity immediately reverses (hard reversal) the line polarity. For example, to transition from Forward Active mode to Reverse Active mode changes LF[2:0] from 001 to 101. Polarity reversal is accommodated in the OHT ...
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... Figure 34. Two-Wire Impedance Simplified 3.18.1. Impedance Synthesis Initialization and Control The Si322x utilizes a digital IIR filter to implement SLIC impedance synthesis. Under normal operation, the Si322x state machine controls the clocks to this filter automatically such that the filter clocks are turned OFF during those times when the filter is not required ...
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... The Dual ProSLIC devices provide a transhybrid balance function via a digitally-programmable balance filter block. (See “H” block in Figure 11.) The Dual ProSLIC devices implement an 8-tap FIR filter and a second-order IIR filter, both running kHz sample rate. These two filters combine to form a digital replica of the reflected signal (echo) from the transmit path inputs ...
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Si3220/25 Si3200/02 8 kHz Clock OSCnEN Zero 16-Bit Cross Modulo OSCnTA Logic Expire Counter OSCnTI Expire OSCnTA OSCnTAEN OSCnTI OSCnTIEN *Tone Generator 1 Only n = "1" or "2" for Tone Generator 1 and 2, respectively 3.20.2. Oscillator Frequency and ...
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To enable automatic cadence for tone generator 1, define the OSC1TA and OSC1TI registers and set the OSC1TAEN and OSC1TIEN bits. This enables each of the timers to control the state of the oscillator enable bit, OSC1EN. The 16-bit counter ...
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Si3220/25 Si3200/02 OSC1EN ... ... 0,1 , OSC1TA ENSYNC1 Tone Gen. 1 Signal Output Figure 36. Tone Generator Timing Diagram First Ring Burst Message Message Parameter 1 Type Length Message Header Parameter Type Figure 37. On-Hook Caller ID Transmission Sequence ...
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... The register and RAM locations for caller ID generation are listed in Table 37. Caller ID data is entered into the 8-bit FSKDAT register. The data byte is double buffered so that the Dual ProSLIC can generate an interrupt indicating the next data byte can be written when processing begins on the current data byte. The caller ...
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Si3220/25 Si3200/02 3.22. Pulse Metering Generation The Si3220 offers an additional tone generator to generate tones above the audio frequency band. This oscillator generates billing tones that are typically 12 kHz or 16 kHz. The generator follows the same algorithm ...
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BUF A Figure 38. Pulse Metering Generation Block Diagram 3.23. DTMF Detection On-chip DTMF detection, also known as touch tone, is available in the Si3220 and Si3225 in-band signaling system that replaces the ...
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... A 0xD B 0xE C 0xF D 0x0 3.24. Modem Tone Detection The Dual ProSLIC devices are capable of detecting a 2100 Hz modem tone as described Recommendation V.8. The detection scheme can be implemented in both transmit and receive paths and is enabled by programming the appropriate register bit. The detection scheme should be disabled for power conservation after the modem tone window has passed ...
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A/D converter. One more digital filter, THPF, is available in the transmit path. THPF implements the high-pass attenuation requirements for signals below 65 Hz. ...
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... RESET Figure 40. PLL Frequency Synthesizer 72 3.26. System Clock Generation The Dual ProSLIC devices generate the internal clock frequencies from the PCLK input. PCLK must be synchronous to the 8 kHz FSYNC clock and run at one of the following rates: 256 kHz, 512 kHz, 786 kHz, 1 ...
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... INT pin remains asserted. Si3220/25 Si3200/02 3.28. SPI Control Interface The control interface to the Dual ProSLIC devices is a 4-wire SPI bus modeled after microcontroller and serial peripheral devices. The interface consists of a clock, SCLK, chip select, CS, serial data input, SDI, and serial data output, SDO ...
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Si3220/25 Si3200/02 The control byte has the following structure and is presented on the SDI pin MSB first BRDCST R/W REG/RAM Reserved CID[0] CID[1] CID[2] CID[3] See Table 42 for bit definitions. 7 BRDCST Indicates a broadcast operation ...
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... Figure 41. SPI Daisy-Chain Mode Rev. 1.3 Si3220/25 Si3200/02 SDI0 SDI Channel 0 CS SDI1 Dual ProSLIC #1 SDO Channel 1 SCLK SDITHRU SDI2 SDI Channel 2 CS SDI3 Dual ProSLIC #2 SDO Channel 3 SCLK SDITHRU SDI4 SDI14 SDI Channel 14 CS SDI15 Dual ProSLIC #8 SDO Channel 15 SCLK SDITHRU 75 ...
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Si3220/25 Si3200/02 In Figure 42, the CID field is zero. As this field is decremented (in LSB to MSB order), the value decrements for each SDI down the line. The BRDCST, R/W, and REG/RAM bits remain unchanged as the control ...
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Figures 45 and 46 illustrate WRITE and READ operations to register addresses via a 16-bit SPI controller. These operations require a 4-byte transfer arranged as two 16-bit words. The absence of CS going high after the eighth bit of data ...
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Si3220/25 Si3200/02 CS SCLK SDI CONTROL SDO Figure 47. RAM Write Operation via an 8-Bit SPI Port CS SCLK SDI CONTROL SDO Figure 48. RAM Read Operation via an 8-Bit SPI Port CS SCLK SDI CONTROL SDO Figure 49. RAM ...
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... PCM Interface The Dual ProSLIC devices programmable interface for the transmission and reception of digital PCM samples. PCM data transfer is controlled by the PCLK and FSYNC inputs, PCM Mode Select, PCM Transmit Start PCMTXLO), and PCM Receive Start Count (PCMRXHI/ PCMRXLO) registers. The interface can be configured to support from 4 to 128 8-bit timeslots in each frame ...
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... HI-Z Figure 53. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS = 10) 3.30. PCM Companding The Dual ProSLIC devices support both µ-255 Law (µ- Law) and A-Law companding formats in addition to Linear Data mode. The data format is selected via the PCMF bits of the PCM Mode Select register. µ-Law ...
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PCLK FSYNC PCLK_CNT DRX MSB DTX HI-Z MSB Figure 54. 16-Bit Linear Mode Example, Timeslots 1 and 2, Long FSYNC Si3220/25 Si3200/ Rev. 1.3 ...
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Si3220/25 Si3200/02 Table 43. µ-Law Encode-Decode Characteristics Segment #Intervals X Interval Size Number 256 128 ...
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Table 44. A-Law Encode-Decode Characteristics Segment #intervals X interval size Number 128 Notes: ...
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... If GCI mode is selected, the following pins must be tied to the correct state to select one of eight subframe timeslots in the GCI frame (described below). These pins must remain in this state while the Dual ProSLIC is operating. Selecting a particular subframe causes that individual Dual ProSLIC device to transmit and receive on the appropriate subframe in the GCI frame, which is initiated by an FSYNC pulse ...
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... Monitor Channel The Monitor channel is used for initialization and setup of the Dual ProSLIC devices also used for general communication with the Dual ProSLIC by allowing read and write access to the Dual ProSLIC devices registers. Use of the monitor channel requires manipulation of the 125 µ ...
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Si3220/25 Si3200/02 FS CH0 Sub-Frame 16 B1 Figure 56. GCI Highway Frame Structure for 16-Bit GCI Mode 1st Byte MX Transm itter MX MR Receiver MR Figure 57. Monitor Handshake Timing 86 125 µ Frame CH1 CH2 8 ...
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... Monitor byte, the Dual ProSLIC signals an abort. For read and write commands, an initial address must be specified. The Dual ProSLIC responds to a read or a write command at this address and then subsequently increments this address after every register access. In this manner, multiple consecutive registers can be read or written in one transmission sequence ...
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... bit calcu lated and tran s m itted on d ata ups tream (D TX) line. MX received d ata dow n s trea lin e. LL: Las t look of m onitor b yte received line. ABT: Abort ind ication to in terna l s ource. Figure 58. Dual ProSLIC Monitor Receiver State Diagram 88 Initial S tate ...
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... MX: MX bit calculated and expected line. MXR : MX bit s am pled line. C LS: C ollis ion w ithin the m onitor data byte line. R QT: R eques t for trans ion from internal s ource. ABT: Abort reques t/indication. Figure 59. Dual ProSLIC Monitor Transmitter State Diagram Si3220/25 Si3200/ Wait A bort ...
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... Si3220/25 Si3200/02 Figures 60 and 61 are example timing diagrams of a register read and a register write to the Dual ProSLIC using the GCI. As noted in Figure 59, the transmitter should always anticipate the acknowledgement of the receiver for correct communication with the Dual ProSLIC. Devices that do not accept this “best case” timing scenario will not be able to communicate with the Dual ProSLIC ...
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... Frame MX Downstream Bit MR Downstream Bit Monitor Data Upstream $FF $FF $FF $FF $FF MX Upstream Bit MR Upstream Bit = Acknowledgement of data reception Figure 61. Example Write to Registers $10 and $11 in Channel 0 of the Dual ProSLIC Si3220/25 Si3200/02 $01 $10 $10 Data to be Data to be written to written to $10 $10 $FF $FF ...
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... Channel A is the source Channel B is the source Upon sending the two-byte CID command, the Dual ProSLIC sends an EOM signal ( for two consecutive frames. When must the Dual ProSLIC signals an abort due to an invalid command. In this mode, only bit C is programmable. ...
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... CI1B Figure 62. SC Channel Structure 3.31.9. Downstream (Receive) SC Channel Byte The first six bits in the downstream SC channel control both channels of the Dual ProSLIC where the C/I bits are defined as follows: CI2A, CI1A, CI0A Used to select operating mode for channel A CI2B, CI1B, CI0B Used to select operating mode for ...
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... C/I Code = Figure 63. Protocol for Receiving C/I Bits in the Dual ProSLIC When the Dual ProSLIC is set to GCI mode at initialization, the default setting ignores the downstream SC channel byte and allows linefeed state commands to be directed through the monitor channel. This default configuration is enabled by initializing the GCILINE bit ...
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... SC channel byte information quickly transfers the most time-critical information from the Dual ProSLIC to the GCI bus. Each upstream SC channel byte transfer from the Dual ProSLIC lasts for at least two consecutive frames to Table 50. Automatic Linefeed State Transitions Initiating Action Automatic Linefeed State Loop closure detected On-hook active → ...
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... SC channel byte includes the required interrupt functions. 3.32. System Testing The Dual ProSLIC devices include a complete suite of test tools to test the functionality of the line card and detect fault conditions present on the TIP/RING pair. Using one of the loopback test modes with the signal generation and measurement tools eliminates the need for per-line test relays and centralized test equipment ...
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... V 300 to 3400 Hz 300 to 3400 Hz Diagnostics mode ringing generation. The Dual ProSLIC devices can generate an internal low-level ringing signal to test for the presence of REN without causing the terminal equipment to ring audibly. This ringing signal can be either balanced or unbalanced depending on the state of the RINGUNB bit of the RINGCON register ...
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... RING,EXT ringing source (Si3225 only) The SLIC diagnostic capability consists of a peak detect block and two filter blocks, one for dc and one for ac. The topology is illustrated in Figure 64. The peak detect filter block reports the magnitude of the largest positive or negative value without sign ...
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... T-G, R-G, or T-R for dc resistance per GR-909 specifications. If the dc resistance is < 150 kΩ considered a resistive fault. To perform this test, program the Dual ProSLIC chipset to generate a constant open-circuit voltage, and measure the resulting current. The resistance is then calculated. ...
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... Knowing the synthesized two-wire impedance of the Dual ProSLIC, the roll-off effect can be used to calculate the ac line capacitance. Ringing voltage verification. Verifies that the desired ringing signal is correctly applied to the TIP/ ...
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... Transconductance Amplifier Resistor Connection. Differential Capacitor. Capacitor used in low-pass filter to stabilize SLIC feedback loops. Common Mode Capacitor. Capacitor used in low-pass filter to stabilize SLIC feedback loops. Component Reference Ground. Return path for differential and common-mode capacitors. Do not connect to system ground. Rev. 1.3 ...
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Si3220/25 Si3200/02 Symbol Pin Number(s) Si3220 Si3225 9 9 IREF 17, 64 17, 64 STIPDCb, STIPDCa 18, 63 18, 63 STIPACb, STI- PACa 19, 62 19, 62 SRINGACb, SRINGACa 20, 61 20, 61 SRINGDCb, SRINGDCa 21, 60 21, 60 ITIPNb, ...
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Symbol Pin Number(s) Si3220 Si3225 28, 52 28, 52 RTRPb, RTRPa 30, 50 30, 50 TRD2b, TRD2a 31, 48 RRDb, RRDa 31, 48 GPOb, GPOa 32, 49 32, 49 BATSELb, BATSELa 35 35 DRX 36 36 DTX 39 ...
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Si3220/25 Si3200/02 Symbol Pin Number(s) Si3220 Si3225 46 46 SDITHRU BLKRNG epad epad GND 104 Input/ Description Output O Serial Data Daisy Chain. Enables multiple devices to use a single CS for serial port con- trol. ...
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Pin Descriptions: Si3200/2 Pin #(s) Symbol Input/ Output 1 TIP I — 3 RING I/O 4 VBAT — — BATH 6 V — BATL 7 GND — 8 VDD — 9 BATSEL I ...
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Si3220/25 Si3200/02 Pin #(s) Symbol Input/ Output 12 IRINGN I 13 IRINGP I 14 THERM O 15 ITIPN I 16 ITIPP I epad GND 106 Description Negative RING Current Control. Connect to the IRINGN lead of the Si3220 or Si3225. ...
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... Package Outline: 64-Pin TQFP Figure 65 illustrates the package details for the Dual ProSLIC. Table 53 lists the values for the dimensions shown in the illustration. Symbol Millimeters Min Nom A — — A1 0.05 — A2 0.95 1.00 b 0.17 0.22 c 0.09 — 12.00 BSC D1, E1 10.00 BSC D2 ...
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Si3220/25 Si3200/02 7. Package Outline: 16-Pin ESOIC Figure 66 illustrates the package details for the Si3200/2. Table 54 lists the values for the dimensions shown in the illustration Seating Plane Figure 66. 16-Pin ...
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... Si3220/Si3225 System Demonstration Kit User's Guide” “AN74: SiLINKPS-EVB User's Guide” “AN75: Si322x Dual ProSLIC Demo PBX and GR-909 Testing Software Guide” “AN86: Ringing / Ringtrip Operation and Architecture on the Si3220/Si3225” “AN88: Dual ProSLIC Line Card Design” ...
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... Si3220/25 Si3200/02 9. Dual ProSLIC Selection Guide Part Number Description Si3200-X-FS 100 V Linefeed IC Si3200-X-GS 100 V Linefeed IC Si3202-X-FS 125 V Linefeed IC Si3202-X-GS 125 V Linefeed IC Si3220-X-FQ Dual ProSLIC Si3220-X-GQ Dual ProSLIC Si3225-X-FQ Dual ProSLIC Si3225-X-GQ Dual ProSLIC Notes: 1. “X” denotes product revision. 2. Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel. ...
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... Added note to Tables 15 and 17 to clarify SDO and DTX pulldown requirements when multiple Si3220/25s are connected to the same SPI or PCM bus. Updated "9. Dual ProSLIC Selection Guide" on page 110. Revision 1.2 to Revision 1.3 Added Si3202 125 V linefeed IC. Si3220/25 Si3200/02 Rev. 1.3 111 ...
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... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and ProSLIC are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...