XC95144XL-5TQ100C Xilinx Inc, XC95144XL-5TQ100C Datasheet - Page 9
XC95144XL-5TQ100C
Manufacturer Part Number
XC95144XL-5TQ100C
Description
CPLD XC9500XL Family 3.2K Gates 144 Macro Cells 178.6MHz 0.35um (CMOS) Technology 3.3V 100-Pin TQFP
Manufacturer
Xilinx Inc
Series
XC9500XLr
Datasheets
1.XC9536XL-10VQG44C.pdf
(18 pages)
2.XC9572XL-10TQG100C.pdf
(1 pages)
3.XC95144XL-10TQG100C.pdf
(12 pages)
Specifications of XC95144XL-5TQ100C
Package
100TQFP
Family Name
XC9500XL
Device System Gates
3200
Number Of Macro Cells
144
Maximum Propagation Delay Time
5 ns
Number Of User I/os
81
Number Of Logic Blocks/elements
8
Typical Operating Supply Voltage
3.3 V
Maximum Operating Frequency
178.6 MHz
Number Of Product Terms Per Macro
90
Memory Type
Flash
Operating Temperature
0 to 70 °C
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
5.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
144
Number Of Gates
3200
Number Of I /o
81
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
3.3V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
122-1250
XC95144XL-5TQ100C
XC95144XL-5TQ100C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC95144XL-5TQ100C
Manufacturer:
Xilinx Inc
Quantity:
10 000
The internal logic of the product term allocator is shown in
Figure
DS054 (v2.5) May 22, 2009
Product Specification
8.
R
From Lower
From Upper
Macrocell
Macrocell
Figure 8: Product Term Allocator Logic
Macrocell
To Lower
Macrocell
To Upper
www.xilinx.com
XC9500XL High-Performance CPLD Family Data Sheet
Product Term
Allocator
Product Term Set
Product Term Clock
Product Term Reset
Product Term OE
1
0
Global Set/Reset
Global Set/Reset
Global Clocks
D/T
CE
DS054_08_042101
S
R
Q
9